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Mon, 02 Feb 2026 02:56:58 -0800 (PST) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a88b4c4665sm143981225ad.64.2026.02.02.02.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Feb 2026 02:56:58 -0800 (PST) From: Taniya Das Subject: [PATCH v2 0/4] Add the support for Glymur Video clock controller Date: Mon, 02 Feb 2026 16:26:49 +0530 Message-Id: <20260202-glymur_videocc-v2-0-8f7d8b4d8edd@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAPGCgGkC/13MQQ6CMBCF4auQWVtCC47oynsYYmgZYBKg2kojI dzdSuLGzST/JO9bwZNj8nBJVnAU2LOdYqhDAqavp44EN7FBZQozqXLRDcs4u3vghqwxQupjUWK rJZ4Q4ujhqOX3Dt6q2D37l3XL7gf5/f6o4p8KUmQCsWxLfTaYa7pa79PnXA/GjmMaD1Tbtn0Ax kG2H7MAAAA= X-Change-ID: 20260123-glymur_videocc-1b5486fb1676 To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona , Konrad Dybcio , Dmitry Baryshkov Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=MNltWcZl c=1 sm=1 tr=0 ts=698082fc cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=fIyPvZiF_eL1qQs3ZgoA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: __E8foWKiUiy2IgNXBjg8kyAAZ_3quC8 X-Proofpoint-ORIG-GUID: __E8foWKiUiy2IgNXBjg8kyAAZ_3quC8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjAyMDA4OCBTYWx0ZWRfXwlDrBDLc2fUg YajxCB5RJzUrvjSsD7Fg1IXBL55mLo8B4kAZ7x7YlHxfiWs1rPZys2olQ6y1wlePch1B48uDGU8 Jj3AeBkdfyinjRRMVt3eFhySusnFtHfczEmfolVP7naPRpO3b4Bk3A3tzs5B8rRPIeJ5s8awML4 vazyIBZl6yU1X+aOSTtDKM2K9iOj7zADqaGOJeYILfSrci2pq50DVcBGYE3aLLO/JdRwa1ThCMn 81P/EdgRZyf9IVTpE6jocNqwCjeOgHaUDLxMKdnzUhuurLL+/vNF4zvott+60DAkhtBx6XFsrLO z7YDpCPAGvUp0/tSRlC9RA6weu0kZdKfQKVKnktLB66tzgu2/3cYoTwmUg4fbmgQUqkxST6cai2 7G4gzx670FxinpamiYdWfWOHOdDjr2MVg/bIvPqJ3uscRgU0NnS1PKsx+GBU5xZkEcISIEuw5TE jzt8egDpNh4M/Yg1+Ag== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-02_03,2026-01-30_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602020088 Support the Video clock controller for Glymur Qualcomm SoC. Changes in v2: - Split the GCC reset clock additions in a separate patches[Dmitry]. - Link to v1: https://lore.kernel.org/r/20260124-glymur_videocc-v1-0-668f8b9c63be@oss.qualcomm.com Signed-off-by: Taniya Das --- Taniya Das (4): dt-bindings: clock: qcom: Add GCC video axi reset clock for Glymur dt-bindings: clock: qcom: Add video clock controller on Glymur SoC clk: qcom: gcc-glymur: Add video axi clock resets for glymur clk: qcom: videocc-glymur: Add video clock controller driver for Glymur .../bindings/clock/qcom,sm8450-videocc.yaml | 3 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-glymur.c | 1 + drivers/clk/qcom/videocc-glymur.c | 533 +++++++++++++++++++++ include/dt-bindings/clock/qcom,glymur-gcc.h | 1 + include/dt-bindings/clock/qcom,glymur-videocc.h | 45 ++ 7 files changed, 593 insertions(+) --- base-commit: a0c666c25aeefd16f4b088c6549a6fb6b65a8a1d change-id: 20260123-glymur_videocc-1b5486fb1676 Best regards, -- Taniya Das