[PATCH RFC 5/8] arm64: dts: qcom: Remove inexistent TCSR_CC

[Konrad Dybcio <konradybcio@kernel.org>]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

On SM8750 specifically, the block which provides various reference
clocks does *NOT* live inside TCSR, but rather TLMM.

With the former now being able to properly expose them, switch over to
the proper source.

Now, the TCSR still exists as a block for various tunables and
switches, however the prior misuse resulted in its 8750-specifc
compatible being already in use. With it freed up, it is now free again
to be described properly.

Fixes: 068c3d3c83be ("arm64: dts: qcom: Add base SM8750 dtsi")
Cc: <stable+noautosel@kernel.org> # complex dependencies, no immediate gain
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index f56b1f889b85..0c034ba0517f 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -2727,7 +2727,7 @@ usb_hsphy: phy@88e3000 {
 			compatible = "qcom,sm8750-m31-eusb2-phy";
 			reg = <0x0 0x88e3000 0x0 0x29c>;
 
-			clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>;
+			clocks = <&tlmm TCSR_USB2_CLKREF_EN>;
 			clock-names = "ref";
 
 			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
@@ -2742,7 +2742,7 @@ usb_dp_qmpphy: phy@88e8000 {
 			reg = <0x0 0x088e8000 0x0 0x4000>;
 
 			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
-				 <&tcsrcc TCSR_USB3_CLKREF_EN>,
+				 <&tlmm TCSR_USB3_CLKREF_EN>,
 				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
 				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 			clock-names = "aux",
@@ -3063,6 +3063,8 @@ tlmm: pinctrl@f100000 {
 			compatible = "qcom,sm8750-tlmm";
 			reg = <0x0 0x0f100000 0x0 0x102000>;
 
+			clocks = <&rpmhcc RPMH_CXO_CLK>;
+
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 
 			gpio-controller;
@@ -3074,6 +3076,8 @@ tlmm: pinctrl@f100000 {
 			gpio-ranges = <&tlmm 0 0 216>;
 			wakeup-parent = <&pdc>;
 
+			#clock-cells = <1>;
+
 			hub_i2c0_data_clk: hub-i2c0-data-clk-state {
 				/* SDA, SCL */
 				pins = "gpio64", "gpio65";
@@ -3564,16 +3568,6 @@ data-pins {
 			};
 		};
 
-		tcsrcc: clock-controller@f204008 {
-			compatible = "qcom,sm8750-tcsr", "syscon";
-			reg = <0x0 0x0f204008 0x0 0x3004>;
-
-			clocks = <&rpmhcc RPMH_CXO_CLK>;
-
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
 		stm@10002000 {
 			compatible = "arm,coresight-stm", "arm,primecell";
 			reg = <0x0 0x10002000 0x0 0x1000>,
@@ -4818,7 +4812,7 @@ pcie0_phy: phy@1c06000 {
 
 			clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
 				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
-				 <&tcsrcc TCSR_PCIE_0_CLKREF_EN>,
+				 <&tlmm TCSR_PCIE_0_CLKREF_EN>,
 				 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
 				 <&gcc GCC_PCIE_0_PIPE_CLK>;
 			clock-names = "aux",
@@ -4849,7 +4843,7 @@ ufs_mem_phy: phy@1d80000 {
 
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
-				 <&tcsrcc TCSR_UFS_CLKREF_EN>;
+				 <&tlmm TCSR_UFS_CLKREF_EN>;
 
 			clock-names = "ref",
 				      "ref_aux",

-- 
2.52.0