From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from casper.infradead.org (casper.infradead.org [90.155.50.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5E7917A316 for ; Mon, 2 Feb 2026 12:54:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.50.34 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770036876; cv=none; b=NsczGN0P0Bto9DoDbxfQAg667r+rXU4dZ/41hmlI6pNgxgCyvOZ8NV24TBg62uJn5rVXxFAwE4S8f3eSzI07+GZDMH4s9ret7J0j46xa6W0GLUpfprpIR1yNqvoi38jtDTmEoK5AG7tKbgc3WVCvn7zf0ObQCFpBkXgWSEs84QM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770036876; c=relaxed/simple; bh=IEedXsPQcDbA+wiPrI93P0oK1XzSa1xcP91FqSUOZK8=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=U+jjBgafwG7m+550zs77SpDuoZhCvPR43n/TlqXX/nbuYzwSVAufAe2lN0lzp4C6s5kujvzhpdzw/wphiW51hwSh3L3R5cxIlVu58YR7oSHDvnGsyaoA6cR4avEvRUQatowrNCMnktKb8BoZx8GchOQRUz+fWDw0CKPP7zOKk8E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org; spf=none smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=Zi6IExOj; arc=none smtp.client-ip=90.155.50.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="Zi6IExOj" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=zBWzUrIvZV7MRXNxWrW39j7pY5H91jL8WVm3XWjW32Y=; b=Zi6IExOjFwh3kvLJ9/u3EIop/d 0Ayxatc/BuJq1HRDQDbryiTbX88oD8FFQSTVorrioMFKyO39PTa83ydsr/9zCFyar+h+cLau9Bpai dQQtrjdujFNgTbmKpvEVyg+xkB3kOB4xJ9SnwCL6qtrgUsEc05LF3MFm1OYELPkcHXVCOh3aDsZrx Ggqe6tyIqZqYd3TErNiZImmxGzN3l8dCxPEk9Jg+SrYhf3bjosdn8DV88gjP15EI7+fmjGt1da5fE Uqu+PqN5Yz9WE8Fe4MPwUrmArcs+twaapTkCnPkoqvCidKJliMgVxAS5klyPUILO1iG807tIxGXHs ai461obg==; Received: from 77-249-17-252.cable.dynamic.v4.ziggo.nl ([77.249.17.252] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.98.2 #2 (Red Hat Linux)) id 1vmtRm-0000000GVNV-3ri8; Mon, 02 Feb 2026 12:54:31 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 7804E300208; Mon, 02 Feb 2026 13:54:30 +0100 (CET) Date: Mon, 2 Feb 2026 13:54:30 +0100 From: Peter Zijlstra To: Mathieu Desnoyers Cc: Thomas Gleixner , LKML , Ihor Solodrai , Shrikanth Hegde , Michael Jeanson Subject: Re: [patch V2 0/4] sched/mmcid: Cure mode transition woes Message-ID: <20260202125430.GD1395266@noisy.programming.kicks-ass.net> References: <20260201192234.380608594@kernel.org> <20260202101424.GB3016024@noisy.programming.kicks-ass.net> <2adfed8a-c844-423e-8638-519db7f8a0cb@efficios.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2adfed8a-c844-423e-8638-519db7f8a0cb@efficios.com> On Mon, Feb 02, 2026 at 06:46:34AM -0500, Mathieu Desnoyers wrote: > On 2026-02-02 05:14, Peter Zijlstra wrote: > > On Mon, Feb 02, 2026 at 10:39:35AM +0100, Thomas Gleixner wrote: > > > > > --- a/kernel/sched/core.c > > > +++ b/kernel/sched/core.c > > > @@ -10445,6 +10445,12 @@ static bool mm_update_max_cids(struct mm > > > /* Flip the mode and set the transition flag to bridge the transfer */ > > > WRITE_ONCE(mc->mode, mc->mode ^ (MM_CID_TRANSIT | MM_CID_ONCPU)); > > > + /* > > > + * Order the store against the subsequent fixups so that > > > + * acquire(rq::lock) cannot be reordered by the CPU before the > > > + * store. > > > + */ > > > + smp_mb(); > > > return true; > > > } > > > @@ -10487,6 +10493,16 @@ static inline void mm_update_cpus_allowe > > > irq_work_queue(&mc->irq_work); > > > } > > > +static inline void mm_cid_complete_transit(struct mm_struct *mm, unsigned int mode) > > > +{ > > > + /* > > > + * Ensure that the store removing the TRANSIT bit cannot be > > > + * reordered by the CPU before the fixups have been completed. > > > + */ > > > + smp_mb(); > > > + WRITE_ONCE(mm->mm_cid.mode, mode); > > > +} > > > > I think this could've been smp_store_release(), but this is the slow > > path so nobody cares and this is nicely symmetric. > > I'm not sure the store-release would work here. What load-acquire > would it pair with ? The purpose here -- per the comment is to ensure the fixup stuff is visible before the TRANSIT bit goes 0, store-release ensures that. That pairs with whatever cares about this barrier now.