From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC64DE555; Tue, 3 Feb 2026 03:31:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770089469; cv=none; b=rUqDjG+7uIH7od0poczYGcvbfXjjr+DPYVzYL+VzYct/3D/v2q2lBd57oYj/54SDT8UycON3vSucwTIB8OBfaLYUrmiAO0ge0RhUjljkUi8zaNmer0uo3clHZVidPLHpko/HyDJY17NLPh48BIQYGxiNMjebrw1gUAZL20cy1wA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770089469; c=relaxed/simple; bh=k9UfBxEpBMAyQjIal6DX1QgxMeA2a7lbB3gZf936jyg=; h=From:Subject:Date:Message-ID:MIME-Version:Content-Type:To:CC; b=MNleuaPjolgwjtLtATc+fHJYu5th9bKeMo4YJs1fJQV68EUfaElhrd5mS6vFdx1yf6/mOtHdUY5amhrCmcjANhONGwozmfZbKjkmnat06h/nCspBHcr2qc8vCfaJutCASzTAJKSqtTmmNQSI7muvh1XsEjQHrVnIUg4Vqootn2c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 3 Feb 2026 11:31:04 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 3 Feb 2026 11:31:04 +0800 From: Jacky Chou Subject: [PATCH RESEND v9 0/3] Add ASPEED PCIe PHY support Date: Tue, 3 Feb 2026 11:30:52 +0800 Message-ID: <20260203-upstream_pcie_rc-v9-0-899ee4efe94e@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" CC: , , , , , Jacky Chou X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1770089464; l=5315; i=jacky_chou@aspeedtech.com; s=20251031; h=from:subject:message-id; bh=k9UfBxEpBMAyQjIal6DX1QgxMeA2a7lbB3gZf936jyg=; b=EGn43uQTbOI9N1h9lbTMvBEP6luBawwp15R3KQCR8G2MmoOpQiVHQMWwZbv+tc+mBKyZhgIkU m7EhY8XLMQlCoMH76KQIO7v2s3FV7M1WxckJyoWbVHDnMXnAmuYQcoK X-Developer-Key: i=jacky_chou@aspeedtech.com; a=ed25519; pk=8XBx7KFM1drEsfCXTH9QC2lbMlGU4XwJTA6Jt9Mabdo= This patch series adds support for the ASPEED PCIe PHY, including device tree bindings and PCIe PHY driver. The patches introduce the necessary device tree nodes. Summary of changes: - Add device tree binding documents for ASPEED PCIe PHY - Update MAINTAINERS for new bindings and driver - Implement ASPEED PCIe PHY driver This series has been tested on AST2600/AST2700 platforms and enables PCIe device enumeration and operation. Signed-off-by: Jacky Chou --- Changes in v9: - Remove '[v8,2/4] ARM: dts: aspeed-g6: Add PCIe RC and PCIe PHY node' and send it separately. - Use FIELD_MODIFY to configure register. - Link to v8: https://lore.kernel.org/r/20251230-upstream_pcie_rc-v8-0-03598cdd80cd@aspeedtech.com Changes in v8: - Update the title of cover letter - Remove 'default y' from Kconfig - Change 'PHY:' to 'phy:' in the title of ASPEED PCIe PHY commit. - Remove unnecessary headers from phy-aspeed-pcie.c. - Add ASPEED PCIe PHY MAINTAINERS - Remove applied patches [v7,2/7] dt-bindings: PCI: Add ASPEED PCIe RC support [v7,5/7] PCI: Add FMT, TYPE and CPL status definition for TLP header [v7,6/7] PCI: aspeed: Add ASPEED PCIe RC driver [v7,7/7] MAINTAINERS: Add ASPEED PCIe RC driver - Link to v7: https://lore.kernel.org/r/20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com Changes in v7: - Add PCIe port into aspeed,ast2600-pci.yaml. - Remove aspeed_pcie_init_ports() and merge aspeed_pcie_port_init() to aspeed_pcie_parse_port() - Refactor aspeed remap pcie addr to aspeed_pcie_map_ranges() - Link to v6: https://lore.kernel.org/r/20251201-upstream_pcie_rc-v6-0-8c8800c56b16@aspeedtech.com Changes in v6: - Refer to pci-cpi-bridge.yaml to update aspeed,ast2600-pcie.yaml and the pcie node of aspeed-g6.dtsi. - 'dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group' have applied, remove it from this version. - Adjust the defnitions in pci.h. - Link to v5: https://lore.kernel.org/r/20251117-upstream_pcie_rc-v5-0-b4a198576acf@aspeedtech.com Changes in v5: - Remove legacy-interrupt-controller and the INTx points to pcie node itself. - Correct bar mapping description and implementation to PCIe address configuration in pcie-aspeed.c driver. - Link to v4: https://lore.kernel.org/r/20251027095825.181161-1-jacky_chou@aspeedtech.com/ Changes in v4: - Remove aspeed,ast2700-pcie-cfg.yaml - Add more descriptions for AST2600 PCIe RC in aspeed,ast2600-pcie.yaml - Change interrupt-controller to legacy-interrupt-controller in yaml and dtsi - Remove msi-parent property in yaml and dtsi - Modify the bus range to starting from 0x00 in aspeed-g6.dtsi - Fixed the typo on MODULE_DEVICE_TABLE() in phy-aspeed-pcie.c - Add PCIE_CPL_STS_SUCCESS definition in pci/pci.h - Add prefix ASPEED_ for register definition in RC driver - Add a flag to indicate clear msi status twice for AST2700 workaround - Remove getting domain number - Remove scanning AST2600 HOST bridge on device number 0 - Remove all codes about CONFIG_PCI_MSI - Get root but number from resouce list by IORESOURCE_BUS - Change module_platform_driver to builtin_platform_driver - Link to v3: https://lore.kernel.org/r/20250901055922.1553550-1-jacky_chou@aspeedtech.com/ Changes in v3: - Add ASPEED PCIe PHY driver - Remove the aspeed,pciecfg property from AST2600 RC node, merged into RC node - Update the binding doc for aspeed,ast2700-pcie-cfg to reflect the changes - Update the binding doc for aspeed,ast2600-pcie to reflect the changes - Update the binding doc for aspeed,ast2600-pinctrl to reflect the changes - Update the device tree source to reflect the changes - Adjusted the use of mutex in RC drivers to use GRAND - Updated from reviewer comments - Link to v2: https://lore.kernel.org/r/20250715034320.2553837-1-jacky_chou@aspeedtech.com/ Changes in v2: - Moved ASPEED PCIe PHY yaml binding to `soc/aspeed` directory and changed it as syscon - Added `MAINTAINERS` entry for the new PCIe RC driver - Updated device tree bindings to reflect the new structure - Refactored configuration read and write functions to main bus and child bus ops - Refactored initialization to implement multiple ports support - Added PCIe FMT and TYPE definitions for TLP header in `include/uapi/linux/pci_regs.h` - Updated from reviewer comments - Link to v1: https://lore.kernel.org/r/20250613033001.3153637-1-jacky_chou@aspeedtech.com/ --- Jacky Chou (3): dt-bindings: phy: aspeed: Add ASPEED PCIe PHY phy: aspeed: Add ASPEED PCIe PHY driver MAINTAINERS: Add ASPEED PCIe PHY driver .../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 42 +++++ MAINTAINERS | 8 + drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/aspeed/Kconfig | 14 ++ drivers/phy/aspeed/Makefile | 2 + drivers/phy/aspeed/phy-aspeed-pcie.c | 194 +++++++++++++++++++++ 7 files changed, 262 insertions(+) --- base-commit: 944aacb68baf7624ab8d277d0ebf07f025ca137c change-id: 20251103-upstream_pcie_rc-8445759db813 Best regards, -- Jacky Chou