From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CD162DC350 for ; Wed, 4 Feb 2026 04:56:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770180960; cv=none; b=J5FGTpZ5hQ5ndrT5U1mk/OGlxdCoCnWomAsw+TLptkPSq4VRZp7SXUz8bX9f8A0fgnSp2gOSn9C3pzkVX+6+6a+IDBrYcB8lhzQVjc776NFgycm7AKKni6KU9C3Oa7a+b/8KvjO4aSBKArlY5GWs2A2sgejinbMydR6oSGg48bg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770180960; c=relaxed/simple; bh=K8kS8LTj7SacAhbR8Lm57iCY0N8iq2KDeT/Xb2+vjLw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=eiieLhXxgOVCP2Z4DPM4GInK9jAFwaAPQL2CjGntk3BtFZvn1wqiuGiDbb8CPXsy//27ef379ZUjpEoERmBwjU4gT/l2CWU4SMP5seQDybvMz3CCXSfSn7WPGK4HgGwIlpp0ALBFNYuC0blX0mCfD19mkFHOgVSINxKtFq4rhTU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EdSbGyTX; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EdSbGyTX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1770180960; x=1801716960; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=K8kS8LTj7SacAhbR8Lm57iCY0N8iq2KDeT/Xb2+vjLw=; b=EdSbGyTXEhmZWHh/Nabq3tcfftUXuIeDbwgCxMdRYHh+M/s3U8T+BJkC 7BYUzKZIBKNj/2uYdiHbS+geKrfWm0uzgUQ6zhQirL0FOBWLUKKbqUNiv pr8gi2ZBDvdH2p0QirBQFrl60gAG05r1e4oXeP65vXkXAKCRoTyL+VDe+ htcEsi/NKtgxosMmzmPdUGWAO107jiHfA5z8zHO/AQCi7J7FRi/k5m9Nk ado0rdQ6ixBmfufOy90ulCob52sSw1+jSsAm/lTFwDRgkjX5lGLBfu8nz eW3rGj9mAWI2KD3RQVxfCWRoK68kfbKBkKSZMugWeBhJShHzsk0ycZVBf Q==; X-CSE-ConnectionGUID: JgvZqT2fT0a8oezu+K4i4g== X-CSE-MsgGUID: b00MgHIYTmurbd6wRqRvZg== X-IronPort-AV: E=McAfee;i="6800,10657,11691"; a="70382585" X-IronPort-AV: E=Sophos;i="6.21,272,1763452800"; d="scan'208";a="70382585" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2026 20:56:00 -0800 X-CSE-ConnectionGUID: U8O4G4VkRhiTWmO+8Oi4kA== X-CSE-MsgGUID: KGpyjR7UQ8WugpKpjJ1iqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,272,1763452800"; d="scan'208";a="214757473" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by fmviesa004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2026 20:55:59 -0800 Date: Tue, 3 Feb 2026 21:02:05 -0800 From: Ricardo Neri To: Thomas Gleixner Cc: Tony Luck , Dave Hansen , "Rafael J. Wysocki" , Reinette Chatre , Dan Williams , Len Brown , Andi Kleen , Stephane Eranian , "Ravi V. Shankar" , Ricardo Neri , linuxppc-dev@lists.ozlabs.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Alexander Graf Subject: Re: [PATCH v7 00/24] x86: Implement an HPET-based hardlockup detector Message-ID: <20260204050205.GA31059@ranerica-svr.sc.intel.com> References: <20230301234753.28582-1-ricardo.neri-calderon@linux.intel.com> <20230413035844.GA31620@ranerica-svr.sc.intel.com> <874inx4y4m.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <874inx4y4m.ffs@tglx> User-Agent: Mutt/1.9.4 (2018-02-28) On Tue, Feb 03, 2026 at 04:58:49PM +0100, Thomas Gleixner wrote: > On Wed, Apr 12 2023 at 20:58, Ricardo Neri wrote: > > Hello, checking if there is any feedback on these patches that I plan to > > send to the x86 maintainer. > > Seems this completely fell through the cracks. Alexander reinvented this > recently with all mistakes made before, which made me come back to this. > > This needs to be respun against current mainline. Sure, I will rebase it on mainline. > Most rejects for the x86 preparatory patches are trivial, I am going through your feedback and will update the series as needed. > just the AMD IOMMU code has changed significantly. > I haven't tried to apply the core watchdog stuff at all. I'll look into the needed changes. > > I'll go through the x86/HPET side quickly and comment on what might need > to be still address. Thank you!