From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from r3-17.sinamail.sina.com.cn (r3-17.sinamail.sina.com.cn [202.108.3.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67927354AE4 for ; Thu, 5 Feb 2026 06:37:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=202.108.3.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770273455; cv=none; b=VX2Htx1tGEJ8QCHy1lZca65ox0PQAuW/tFN/cg9JlmLkOpDHtbHk+Wk0Ib/y8lVyt4sHIOfSUnraQR2Tt5FDQONWtPPQpnGJS4uMXlWhLc3FPrcHvKvTXPsvY8wv3w2t2K6GDp5WuHJwSAPVm4qDhR49iqo91BbKrOgYOxh5qqs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770273455; c=relaxed/simple; bh=F9yROrMuEosIgXk6EW8qGaSAXD49xm7LDlS3flZrPTM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Aw7feyMFhty1XRlH4WglP/X3+1L4FCQv71ATXHVDS6wOqLGW+LlXWzUG+LSA0vtxZ94npB6L1cflsp3IeCCPWxkbJiT5iuhaO9pqILR6uzEFj+flCzQFbwcLCKdZYlJPPiVDi+tournbKy12jhna29HF42NQEGSxdAHXvsTInS0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sina.com; spf=pass smtp.mailfrom=sina.com; dkim=pass (1024-bit key) header.d=sina.com header.i=@sina.com header.b=oAXH/kZ6; arc=none smtp.client-ip=202.108.3.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sina.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sina.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=sina.com header.i=@sina.com header.b="oAXH/kZ6" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sina.com; s=201208; t=1770273453; bh=LdiJxpLYzcT9fGAHQaSutI6XaeTYdER8GN0l0vxTCBI=; h=From:Subject:Date:Message-ID; b=oAXH/kZ6NJyz1/xyzZ86214qC0nlFT3en1qo/MK4qd+hvmQKOCo7FL7qbtgpyrkIF Sdsk+PReVL8kulO2x2jeGGjzsgsixNPJzQ4r2Vs2EXTuTo6aErPv9xB0dDD6PhUf3O tYN7LR2P++RKBZVWFlm6QRo/jMPviq0bLBbVAbtw= X-SMAIL-HELO: localhost.localdomain Received: from unknown (HELO localhost.localdomain)([114.249.62.144]) by sina.com (10.54.253.34) with ESMTP id 69843AA200004C83; Thu, 5 Feb 2026 14:37:24 +0800 (CST) X-Sender: hdanton@sina.com X-Auth-ID: hdanton@sina.com Authentication-Results: sina.com; spf=none smtp.mailfrom=hdanton@sina.com; dkim=none header.i=none; dmarc=none action=none header.from=hdanton@sina.com X-SMAIL-MID: 1831106292085 X-SMAIL-UIID: F22844B53C96402F9DEECCC559396D27-20260205-143724-1 From: Hillf Danton To: =?GBK?B?wazX07qt?= <17317795071@163.com> Cc: tglx@linutronix.de, "Christoph Lameter (Ampere)" , linux-kernel@vger.kernel.org Subject: Re: [Question] Voltage droop from synchronized timer interrupts(tick) on many-core SoCs leads to system instability Date: Thu, 5 Feb 2026 14:37:11 +0800 Message-ID: <20260205063714.2579-1-hdanton@sina.com> In-Reply-To: <775bc4a3.3968.19c2c24a1e5.Coremail.17317795071@163.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Thu, 5 Feb 2026 12:52:04 +0800 (CST) =?GBK?B?wazX07qt?= wrote: > Hi all, > We have observed a critical voltage droop issue on large-core-count SoC platforms (e.g., 64+ cores) that appears to stem directly from the synchronized periodic timer interrupts(tick) in the Linux kernel. > > In our testing and power simulations, we found that: > When all CPU cores enter the timer interrupt handler simultaneously, there is a sharp, instantaneous power surge and continuous power fluctuations during the interrupt handling window (which lasts several microseconds), leading to significant voltage droop. In severe cases, this droop can cause system instability or even prevent the OS from booting. > > We understand that enabling skew_tick=1 effectively mitigates this by staggering the per-CPU tick timers. However, in certain deployment scenarios, modifying any kernel boot parameter—including skew_tick—is not permitted. > > Given this constraint, we would greatly appreciate your insights on the following technical questions: > 1. Why does the timer interrupt path consume so much power and exhibit such large instantaneous variations? Our power simulation shows that the average power during timer interrupt handling is comparable to Dhrystone benchmark. > 2. What is the typical duration of a single timer interrupt handler (tick_nohz_handler, etc.) on a modern x86 or ARM core? Is it generally on the order of a few microseconds? > 3. Beyond skew_tick=1, are there other kernel mechanisms or runtime strategies that could reduce the power impact of synchronized timer events? Are there plans in future kernel versions to address this issue more fundamentally—especially for many-core platforms? > > > Thank you very much for your time and expertise. > Sounds like a known issue, feel free to see the comments in 2025 [1]. [1] Subject: Re: [PATCH] Skew tick for systems with a large number of processors https://lore.kernel.org/lkml/87sejew87r.ffs@tglx/ > > Best regards, > Zihan Lian <17317795071@163.com>