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Thu, 05 Feb 2026 16:23:51 -0800 (PST) X-Received: by 2002:a05:7022:62aa:b0:11b:d4a8:d24d with SMTP id a92af1059eb24-12703ff2045mr430344c88.12.1770337431386; Thu, 05 Feb 2026 16:23:51 -0800 (PST) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1270433ac00sm575694c88.9.2026.02.05.16.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Feb 2026 16:23:50 -0800 (PST) From: Andrew Jones To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Conor Dooley , Guodong Xu , Charlie Jenkins , Charlie Jenkins , Samuel Holland Subject: [RFC PATCH v1 00/11] riscv: hwprobe: Introduce rva23u64 base behavior Date: Thu, 5 Feb 2026 18:23:38 -0600 Message-ID: <20260206002349.96740-1-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA2MDAwMSBTYWx0ZWRfX2Vx37WvVjPqc 13VbrobAWEeKteV3z/wYt8qEalgAcazXtG0mxoeohN+Km+sQXb/9tcHcVdBrwCN6NeSInPbJ6xt /RNwYdXDT0beHxO1aolWAwj/SbGtTra6cq9SNAl5CNt5Q09GHA/NTiIuIV10UkOH7uQAfpUAPOF b/p8uBeZ06wuZeddHN07JOsk6cVQOLPOG1tIFNbmZ8TxDVmtqXDhqdyxHPbfH8FvZjMayYB3XYh 5/yiMJbai4UpKhrxEJlS8Erxkrk73A7PRV/B01QwsOwadVpJ+XDh0OThj0jqCIT5DzHn4ZHPp/r CCJT9kuRrBRX/3SyvxYQUIExpzlZIp96l/J9q+5XV+Y25pgXbA63u2df8GXnc56MBo6W+r3nwut lsFLSS+eLXB9/NaxoEJbaUdFz6MVyIyJZ6Ce6Cg8ZQDK6yCxY5slKBfg/TBt+hRmmu3a5W7Dpcl YXLjSosx5RonzHcyQhQ== X-Proofpoint-GUID: M-oBhdZaf4cVupZQWlWiHe37rTJsNjdw X-Authority-Analysis: v=2.4 cv=e4kLiKp/ c=1 sm=1 tr=0 ts=69853498 cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=cvcws7F5//HeuvjG1O1erQ==:17 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=8arYDEdLfb4oE3fV1TAA:9 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-ORIG-GUID: M-oBhdZaf4cVupZQWlWiHe37rTJsNjdw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-05_06,2026-02-05_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 clxscore=1015 adultscore=0 malwarescore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602060001 Users need a way determine that their harts conform to rva23u64 that isn't error-prone. While patches 2 and 6 make it possible to determine, it requires a bunch of probes and checks themselves (see patch9 for the recipe). This RFC proposes adding an RVA23U64 hwprobe base behavior (patch8) allowing easy determination. It also proposes adding the bases to /proc/cpuinfo (patches 10 and 11) -- but those two patches are probably even more RFCy than the hwprobe proposal... The first three patches have been posted previously by their respective authors and are currently under active review (except patch2 which appears to have gotten lost in the shuffle). I've collected these patches into the series since they're necessary for the base and because I wanted to repost patch2 and patch3 with some changes. patch4 and patch6 expose more extensions to userspace. patch9 adds a consistency test for the new hwprobe base behavior bit. Thanks, drew Andrew Jones (8): riscv: Add B to hwcap riscv: hwprobe.rst: Replace tabs with spaces riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to hwprobe riscv: Export have_user_pmlen* booleans riscv: hwprobe: Introduce rva23u64 base behavior riscv: selftests: hwprobe: Check rva23u64 consistency riscv: /proc/cpuinfo: Add rva23 bases to output riscv: /proc/cpuinfo: Also output rva20 and rva22 isa bases Charlie Jenkins (1): riscv: Standardize extension capitilization Jesse Taube (1): RISC-V: Add Zicclsm to cpufeature and hwprobe Paul Walmsley (1): riscv: hwprobe: add support for RISCV_HWPROBE_KEY_IMA_EXT_1 Documentation/arch/riscv/hwprobe.rst | 42 ++- arch/riscv/include/asm/cpufeature.h | 14 + arch/riscv/include/asm/hwcap.h | 23 +- arch/riscv/include/asm/hwprobe.h | 3 +- arch/riscv/include/asm/switch_to.h | 4 +- arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/include/uapi/asm/hwprobe.h | 9 +- arch/riscv/kernel/cpu.c | 38 +++ arch/riscv/kernel/cpufeature.c | 168 ++++++++++-- arch/riscv/kernel/process.c | 12 +- arch/riscv/kernel/sys_hwprobe.c | 249 +++++++++++++----- arch/riscv/kvm/main.c | 2 +- arch/riscv/kvm/vcpu_fp.c | 28 +- arch/riscv/kvm/vcpu_onereg.c | 22 +- arch/riscv/kvm/vcpu_vector.c | 14 +- .../testing/selftests/riscv/hwprobe/hwprobe.c | 112 +++++++- .../selftests/riscv/hwprobe/which-cpus.c | 20 +- 17 files changed, 610 insertions(+), 151 deletions(-) -- 2.43.0