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Sat, 07 Feb 2026 02:28:10 -0800 (PST) From: Guodong Xu Subject: [PATCH 0/8] riscv: Add cpufeature parsing and hwprobe export for RVA23 extensions Date: Sat, 07 Feb 2026 18:27:54 +0800 Message-Id: <20260207-isa-ext-parse-export-v1-0-a64d3a8bc20a@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAKsTh2kC/y2NQQ6CMBBFr9J07Zi2ICgxxnsYFqWMOgugdgohM dzdAu7mzc9//ysZAyHLSnxlwImYhj6BPgjp3rZ/IVCbWBplCqV1AcQWcI7gbWBMlx9CBJWXTim VoTZOpqoP+KR50z7qnQN+xmSP+1M2NrXd0HUUK9Gvwn3BZGu/Q2a7bVfi+g9OwKPvtm1qYTKgQ GPWXEqdu3Oh7oHYcbThmKw3WS/LDxZj1D3cAAAA X-Change-ID: 20260116-isa-ext-parse-export-047c0003e12c To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Jonathan Corbet , Shuah Khan , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.2 Complete the previous series [1] (Patch 6-9), which added DT bindings for extensions mandatory in the RVA23 Profile, by adding cpufeature parsing and hwprobe exports. This patchset is organized so that cpufeature parsing and hwprobe export (when needed) are grouped together. Patches 1-2: B extension Patches 3: Enforce dependency checking for Ziccrse. Patches 4-6: Handle the RVA23U64 extensions, namely Za64rs, Ziccamoa, Ziccif, Zicclsm. Patches 7-8: Handle the RVA23S64 extensions, namely 1) Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl, 2) Sha and its comprised sub-extensions. Noted that among all these extensions, I chose to hwprobe only three: B, Ziccif and Zicclsm. My observation is all recently merged hwprobe extensions (such as Zaamo, Zicntr, Zicbom) expose instructions or CSR that userspace directly executes, or hints for userspace prefetch. Whereas Za64rs and Ziccamoa are named features, currently I don't see a need for userspace to hwprobe them. They can be added later if a concrete userspace use case emerges. Zicclsm is hwprobe exported, previous LKML discussion can be found here: Conor Dooley noted the need for "bindings, detection and hwprobe key for Zicclsm" [2] after Palmer's misaligned access clarification [3]. Ziccif guarantees atomic instruction fetches for naturally aligned instructions. Exposing it through hwprobe allows userspace performing concurrent code modification (CMODX) to confirm the underlying hardware guarantee at runtime. See Documentation/arch/riscv/cmodx.rst [4] for background. The B extension hwprobe bit uses a system-wide check against the global ISA bitmap, following the same pattern as C in hwprobe_isa_ext0(). Zicclsm and Ziccif use the per-CPU EXT_KEY() mechanism, consistent with individual extension exports. This series is based on next-20260123, plus the sump patchset. Tested on SpacemiT K3 PICO ITX board, checked both cat /proc/cpuinfo and a hwprobe userspace testing stub. Link: https://lore.kernel.org/all/20260110-k3-basic-dt-v4-0-d492f3a30ffa@riscstar.com/ [1] Link: https://lore.kernel.org/all/20240524-ruckus-trickily-1cda26c1a455@spud/ [2] Link: https://lore.kernel.org/all/20240524185600.5919-1-palmer@rivosinc.com/ [3] Link: https://lore.kernel.org/all/20250407180838.42877-12-andybnac@gmail.com/ [4] Signed-off-by: Guodong Xu --- Guodong Xu (8): riscv: cpufeature: Add parsing for B riscv: hwprobe: Add support for probing B riscv: cpufeature: Enforce Ziccrse dependency on Zalrsc riscv: cpufeature: Add parsing for Za64rs, Ziccamoa, Ziccif, and Zicclsm riscv: hwprobe: Add support for probing Zicclsm riscv: hwprobe: Add support for probing Ziccif riscv: cpufeature: Add parsing for Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl riscv: cpufeature: Add parsing for Sha and its comprised extensions Documentation/arch/riscv/hwprobe.rst | 11 ++++++ arch/riscv/include/asm/hwcap.h | 18 ++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 3 ++ arch/riscv/kernel/cpufeature.c | 63 ++++++++++++++++++++++++++++++++++- arch/riscv/kernel/sys_hwprobe.c | 5 +++ 5 files changed, 99 insertions(+), 1 deletion(-) --- base-commit: 4af4e95edc37ae54f64cbd75b46f16ce15f3a6b8 change-id: 20260116-isa-ext-parse-export-047c0003e12c prerequisite-message-id: <20260125-supm-ext-id-v2-0-1e3b9714c860@riscstar.com> prerequisite-patch-id: f10e134f9f9291ace47876fa4b2171094838a40b prerequisite-patch-id: 59a67878b96d6de42a9bad35fc610ef10dabff55 prerequisite-patch-id: 30a3e1b50fc95ab5a521f4dab693d914713992f2 Best regards, -- Guodong Xu