From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4395E369209 for ; Mon, 9 Feb 2026 10:55:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770634531; cv=none; b=mQz3b/i0K6jkH5z5e5dkNpoNthEDNE4+8iNfl+7R40qoPdMSlnthvzVEUy/QNIU89yfFnZvRFFEncmvTvDrBxcXOBN8vc1aHDnRVD4TkyVvKDuMJIei15yAhjgQxZiqjWlzMS4TfIMwtGVl9pR4vfWoYumKYMalW62Cutkw0pEg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770634531; c=relaxed/simple; bh=2FWZb65X8mx18YH9h8vMRViW9qAP67jaLh6l/pLRM98=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=uDjz34tbxYTE1fri4+FlUApjFvLTufVqhX4XQ7ydJzOggMGTBbffJYfvn2z+yaMRL3g/3T6nNWWznGzFyuI726iV90+n4YsNeeKocd4AQiRk9ONaZXc/5ffkkdY0lesAsOLr7Wppgcqn3rdqYx3bC2Tq+FMUz28RIPNsBPaeRlM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=V2f8s4QP; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=gBBwbs6W; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="V2f8s4QP"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="gBBwbs6W" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 619AW13o2381283 for ; Mon, 9 Feb 2026 10:55:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:message-id:mime-version :subject:to; s=qcppdkim1; bh=WK0ylVF4GwQX20f4H+s8CJYlFpp8VJaq11P Zdrcjft8=; b=V2f8s4QPfNIBmLm6u/ozo1qJQcDmFYmrPYaI7FjJMG3pwNtVhQp eaHn+tJP/tgGa9LTiu1oFbmTz2CgrFlJVH1DPBq0ZcU6QcythTYBPswHLMUrvBXF teJM7h48kpU5MDXmOcXeqIAcVhI5lb89Bx+xulfzLvG4Z99VMGtDGe6T2+zAFcax Q8o6fF8HTRXV7k0F2M1Kq52YsQ5xAI86QVVYLsciK+Su67778gyl5PKn6Cc8ZlNI hfoIAdy9NcD1R37UODQhiknNOGqtQDVO6CfW2YlKXuVEbCtN9DetF+zunjcyS55R ESCzTcDfRtWSPiIbmaVL+VwtBb/8VorrPIA== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4c78gds9s8-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 09 Feb 2026 10:55:30 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c6dded42ec4so1340203a12.2 for ; Mon, 09 Feb 2026 02:55:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1770634530; x=1771239330; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=WK0ylVF4GwQX20f4H+s8CJYlFpp8VJaq11PZdrcjft8=; b=gBBwbs6W+0Jv4UtLHNk8J/slvIyPexwsRglnSApAcU6Fu5EZdKK9AqQpZTAz66Ns+q KN+PSr4h4Pavjq0OzLs+yr68oXab4NGaWRXaxAyDtrBv8+JVkcr4yRC0wNaVNwvW44eC tSIOMfLA3iDK2HR+b+SL3FnKzAeaSgyN+3BnP/lE/1O+R80pMYZC1jDMefdvs+oPP18h 5NUteknldb/L4e5i1g63vPtgiE2JbT6vPA4n0Da6xNirV77XZ/aUPwl1MYJ3oMUeO+CM 70X+TSoDGKqXzA88JrAYxhmDUUYQ74dWSz5zIAOamG7n6VXj5EeDsrBKWyJJ9hQTbN0x sZvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1770634530; x=1771239330; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=WK0ylVF4GwQX20f4H+s8CJYlFpp8VJaq11PZdrcjft8=; b=uiACbBFwsNDJtrSKRnfj0WZKdDC1tsZWV2CVPkqylWnesn0TJrZnBm5bIOAVcR7UEj oIeTQKmO+E04uXi7ndqTnYMGoZSSSs2O0PWw1R3IRLWOR8SZ+nqqEIo2uSBPCyz9FBYi NkVvNR+fdU+isgppa1Zux0zkQKZt2ADdvncl8wskKg7AZofc0mHRtj0T+6vt9roK0d8I o/9RNac60V29CafABHhS9SB2+s/z9aziFlDBLu/3Bdxm7KKMeD0FNiew9z5G9xfXfipZ T6i58BTdrgxKIlxzy+P4D+GAnJ9kkdH/ztvQnnaEfP9lqYIEy6XvCpdz0o7friAPliAk jLbQ== X-Forwarded-Encrypted: i=1; AJvYcCUG5FwEl9PtLzqbmDPb1Ca1LztLhNrLpUrDGNtq3yZi0l4+RSF5m21HAjJZ+NOmUntanpajkCDu1f+C/Rg=@vger.kernel.org X-Gm-Message-State: AOJu0Yz3RnY/SI8YyPsgFJjOfM1qJ9E6PyD9OdIAIl7tIQT+Q3+B0xf7 PVnh9uWmvEQJ2PXfNQK/zpGNkG7CYN9gBS45tSNp/acskwLSTS+TlrPqIf9K3zSt6NU1Uz17iyM GULFNBVDO8XfMpm1dPa10fNhYhdpORGsPCLaztJqt4sbUyRAHedrwIqDI5pmjaoEHgz8= X-Gm-Gg: AZuq6aKT4lW/fUyJEYTAH0wio/4nBWJ15+4PYUlip6E6K4zAy5OBEaQmuHiTdIvKbF5 EZ/zveb4bTI17wGG/w9nAf+hLxbJyJXwHckoM3/rHUr+AqSQOhs+VvksxUkdotmOpEY7m/wC+le B/lfuJYSNu7inY+7Rj0UwKPDR79V4qKwvFk229OCS2CWi5HvPwHrkdGc/qn3Imavon4dIVKInOz pGAMKVzatg/7kzfvnDZkCjQTz7ZMuv8k1GOWpUbMhdGw2zOvCrDyQ+PRQBQjNpCfogCslTCDbRU LqvJ/UDGupQ+Jog34T9zMERHyyUyHYZZ6wmnpTU1KdSVhLb7dDDKpsaewazhojJIf9j8vKakbUC Pr0je/DHAyTEPYYSWi9JRGf2GOXblFr60+YUCFftDt2YN X-Received: by 2002:a05:6a20:d524:b0:2bf:183c:ac86 with SMTP id adf61e73a8af0-393ad00062amr10309848637.25.1770634529445; Mon, 09 Feb 2026 02:55:29 -0800 (PST) X-Received: by 2002:a05:6a20:d524:b0:2bf:183c:ac86 with SMTP id adf61e73a8af0-393ad00062amr10309818637.25.1770634528866; Mon, 09 Feb 2026 02:55:28 -0800 (PST) Received: from hu-jprakash-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c6dcb5e5f6bsm8358837a12.20.2026.02.09.02.55.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Feb 2026 02:55:28 -0800 (PST) From: Jishnu Prakash To: jic23@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, lumag@kernel.org, dmitry.baryshkov@oss.qualcomm.com, konradybcio@kernel.org, daniel.lezcano@linaro.org, sboyd@kernel.org, amitk@kernel.org, thara.gopinath@gmail.com, lee@kernel.org, rafael@kernel.org, subbaraman.narayanamurthy@oss.qualcomm.com, david.collins@oss.qualcomm.com, anjelique.melendez@oss.qualcomm.com, kamal.wadhwa@oss.qualcomm.com Cc: rui.zhang@intel.com, lukasz.luba@arm.com, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, cros-qcom-dts-watchers@chromium.org, jishnu.prakash@oss.qualcomm.com, quic_kotarake@quicinc.com, neil.armstrong@linaro.org, stephan.gerhold@linaro.org Subject: [PATCH V11 0/4] Add support for QCOM SPMI PMIC5 Gen3 ADC Date: Mon, 9 Feb 2026 16:24:34 +0530 Message-Id: <20260209105438.596339-1-jishnu.prakash@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA5MDA4OSBTYWx0ZWRfX/SNNsSLY++q5 A/rDHXVoJseDqKoG/Dvf58NbE4SOWB1OLFnC7hZm7lY0uACMt8DxkLJ05kH+6THu4JJHdifnOMf j7YtHkbmZJlRLIrRSx2I4OIK+efa4FkclSqoAdMQ/sqmDGugFsbaOMo4cZ+t1X0ytL2vY7JIwt6 UV8eqkntCYZcJkW47yXfPvO4+v5Elokc+/zbcd3RtfuTRYTKO9LFp3AVu7IT0agX/QjLhZqnDDk RDEO2amwgSPzvPei5HDTaH15ez5Qgp8xGzwUh4MGsuQ4W78PNLEjx766CJ3JXTU7lIAwWJQ4CDc gD0rFZIRQgF8qpPxIF2G0QBgosmFfKIPy4M3N/yWu1VCbKTnc50oo4KTIItyzHPbmIR4N7PSnuW qIwE/Q9uKv9RLkhd4v7C3ogaRzsGyiGUt67I9Xa/G29p8Jfsi3Bzh6eOuQsV+T03Rri1eg3elJV GKagxiBKCzJle6HFFTA== X-Authority-Analysis: v=2.4 cv=Fv0IPmrq c=1 sm=1 tr=0 ts=6989bd22 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=XccleKrqIk_kMzO7r2MA:9 a=x9snwWr2DeNwDh03kgHS:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 26RTqgSIi_940o7FCRptsuxOeAKTp-2S X-Proofpoint-GUID: 26RTqgSIi_940o7FCRptsuxOeAKTp-2S X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-08_05,2026-02-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 adultscore=0 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602090089 PMIC5 Gen3 has a similar ADC architecture to that on PMIC5 Gen2, with all SW communication to ADC going through PMK8550 which communicates with other PMICs through PBS. The major difference is that the register interface used here is that of an SDAM present on PMK8550, rather than a dedicated ADC peripheral. There may be more than one SDAM used for ADC5 Gen3. Each ADC SDAM has eight channels, each of which may be used for either immediate reads (same functionality as previous PMIC5 and PMIC5 Gen2 ADC peripherals) or recurring measurements (same as PMIC5 and PMIC5 Gen2 ADC_TM functionality). In this case, we have VADC and ADC_TM functionality combined into the same module. Patch 1 splits out the common ADC channel properties used on older VADC devices, which would also be reused on ADC5 Gen3, into a common binding file, to be referenced in Gen3 and other ADC binding files. Patch 2 adds bindings for ADC5 Gen3 peripheral. Patch 3 adds the main driver for ADC5 Gen3. Patch 4 adds the auxiliary thermal driver which supports the ADC_TM functionality of ADC5 Gen3. Changes since v10: - Replaced inclusion of device.h header file with forwards declaration of struct device in two files and updated all for() loops to declare and initialize the loop iterator in for() statement as suggested by Jonathan. - Addressed some more comments from Jonathan for some minor style changes. - More details about all changes are present in per-patch change logs. - Link to v10: https://lore.kernel.org/all/20260130115421.2197892-1-jishnu.prakash@oss.qualcomm.com/ Changes since v9: - In patch 4, replaced the break statement within scoped_guard() in tm_handler_work() with return statement to fix the error reported by kernel test robot. - Link to v9: https://lore.kernel.org/all/20260128112420.695518-1-jishnu.prakash@oss.qualcomm.com/ Changes since v8: - Collected Reviewed-by tag from Krzysztof on patch 2. - Dropped the common module (drivers/iio/adc/qcom-adc5-gen3-common.c) as suggested by Dmitry. - Made changes in patches 3 and 4 to simplify auxiliary device structure to use module_auxiliary_driver() as requested by Dmitry. - Updated header files included in all newly added files to follow IWYU (include-what-you-use) principles as requested by Jonathan. - Addressed all remaining comments from Jonathan in patches 3 and 4, for refactoring some code. - More details about all changes are present in per-patch change logs. - Link to v8: https://lore.kernel.org/all/20251127134036.209905-1-jishnu.prakash@oss.qualcomm.com/ Changes since v7: - Based on a discussion with Krzysztof concluded here: https://lore.kernel.org/all/d10e2eea-4b86-4e1a-b7a0-54c55907a605@oss.qualcomm.com/, patch 1 in the previous series is updated to move ADC header files from binding to devicetree folders, as they contain HW constants, not exactly bindings. Earlier in series v7, patches 3 (Gen3 binding) and 4 (driver) were dependent on patch 1, as it updated the location of include/dt-bindings/iio/qcom,spmi-vadc.h, which was used in patches 3 and 4 for Gen3 channel macros. In v8, these macros will be added in other new files, so the former patch 1 will now be a standalone change separate from this series, as the other patches here are no longer dependent on it. - Patches 2/3/4/5 of v7 are now patches 1/2/3/4 in v8. Below comments refer to v7 patch numbers. - Updated description of `reg` property in patch 2 to completely drop mentions of binding file paths, to simplify it and avoid any dependencies with patch 1. - Dropped all ADC channel macro definitions from patch 3, updated binding example correspondingly and fixed formatting inconsistancies in property names, to address Krzysztof's comments. - Addressed all comments from Jonathan in driver patches 4 and 5, for fixing formatting and refactoring some code. - In patch 4, added ADC5 Gen3 channel macros in qcom-adc5-gen3-common.h, for use in main driver file. Also added a check to fail probe in case ADC channel value obtained from devicetree is not among list of supported channels. - More details about all changes are present in per-patch change logs. - Link to v7: https://lore.kernel.org/all/20250826083657.4005727-1-jishnu.prakash@oss.qualcomm.com/ Changes since v6: - Collected Acked-by tags from Jonathan on patches 1, 2 and 3. - Addressed Neil's comment in patch 3. - Updated copyright to yearless one in newly added files, following new internal guidelines. - Addressed all comments from Jonathan on patches 4 and 5 (most importantly for updating auxiliary device cleanup handling to fix memory freeing issues). - More details about all changes are present in per-patch change logs. - Link to v6: https://lore.kernel.org/all/20250509110959.3384306-1-jishnu.prakash@oss.qualcomm.com/ Changes since v5: - Collected Reviewed-by tag from Krzysztof on patch 2. - Addressed all comments from Krzysztof and Jonathan on patch 3. - Addressed all comments from Jonathan on patches 4 and 5. - More details about all changes are present in per-patch change logs. - Link to v5: https://lore.kernel.org/all/20250131183242.3653595-1-jishnu.prakash@oss.qualcomm.com/ Changes since v4: - Split common ADC channel properties out into a separate file to use as ref for ADC5 Gen3 and moved ADC5 Gen3 documentation into a separate file as suggested by reviewers. - Addressed few reviewer comments in driver patches. - Link to v4: https://lore.kernel.org/all/20241030185854.4015348-1-quic_jprakash@quicinc.com/ Changes since v3: - Updated files affected by adc file path change in /arch/arm folder, which were missed earlier. - Added ADC5 Gen3 documentation changes in existing qcom,spmi-vadc.yaml file instead of adding separate file and addressed reviewer comments for all bindings. - Addressed review comments in driver patch. Split out TM functionality into auxiliary driver in separate patch and added required changes in main driver, as suggested by Dmitry. - Link to v3: https://lore.kernel.org/all/20231231171237.3322376-1-quic_jprakash@quicinc.com/ Changes since v2: - Reordered patches to keep cleanup change for ADC files first. - Moved ADC5 Gen3 documentation into a separate file Changes since v1: - Dropped patches 1-5 for changing 'ADC7' peripheral name to 'ADC5 Gen2'. - Addressed reviewer comments for binding and driver patches for ADC5 Gen3. - Combined patches 8-11 into a single patch as requested by reviewers to make the change clearer and made all fixes required in same patch. Jishnu Prakash (4): dt-bindings: iio: adc: Split out QCOM VADC channel properties dt-bindings: iio: adc: Add support for QCOM PMIC5 Gen3 ADC iio: adc: Add support for QCOM PMIC5 Gen3 ADC thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml | 151 +++ .../iio/adc/qcom,spmi-vadc-common.yaml | 84 ++ .../bindings/iio/adc/qcom,spmi-vadc.yaml | 78 +- .../bindings/mfd/qcom,spmi-pmic.yaml | 1 + drivers/iio/adc/Kconfig | 26 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/qcom-spmi-adc5-gen3.c | 860 ++++++++++++++++++ drivers/thermal/qcom/Kconfig | 9 + drivers/thermal/qcom/Makefile | 1 + drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c | 507 +++++++++++ include/linux/iio/adc/qcom-adc5-gen3-common.h | 212 +++++ 11 files changed, 1856 insertions(+), 74 deletions(-) create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c create mode 100644 drivers/thermal/qcom/qcom-spmi-adc-tm5-gen3.c create mode 100644 include/linux/iio/adc/qcom-adc5-gen3-common.h base-commit: 18f7fcd5e69a04df57b563360b88be72471d6b62 -- 2.25.1