From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out30-131.freemail.mail.aliyun.com (out30-131.freemail.mail.aliyun.com [115.124.30.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFD8133D6FA for ; Mon, 9 Feb 2026 12:36:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770640599; cv=none; b=FstVjM7uSTbc5bgIxtUVzIqWKumMJ5oLIDSTmhCfBUvbASRXcyqKBYMc2QCjCh/sxkl7geI7hJQ2pz/OKX2ez7jvaWdUlJhGaGYeyz4WFeHM+kePwxJcjnbiDlzhvGQJMiMmX/AZCxg0TZ8OewIamLk2XkbwwDwgZ8hBAFQOFt4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1770640599; c=relaxed/simple; bh=M0UA/qj17rH9MZ0SDILOKOfR3GJlDE+UuhG5UmT34ic=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fAehkoHpxtp5em0/4mlpONV/17BajlF3ftxLQDRqcRkZ7Qy9AuBiTt28X8avnctK5WWuxFdTFtcp2MMG4DCvmbg0lQZqnloZfSWRn1Ga+I5fh371et42cvbX3F8OFv6SUOW/L0nKd/Auxt+NRrN1exdgbblFhxnd2De0Eb4yVRg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=qTZ7ttqu; arc=none smtp.client-ip=115.124.30.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="qTZ7ttqu" DKIM-Signature:v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1770640595; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=j2mQMotxAbyONBNpxzE2wutnL2uBY8ZDUN3PiY3/Dug=; b=qTZ7ttqu06bAudP2r2uaPBvpi5Pv5R3oKv+dTRJ/h8TP304MAnC3Q335+2dPcbcUNYjV41+AOX7GPlgRcVG1jhAX52ZbYO4t5DhB02gz55T6GTQuFp4LL2tiVZ1XF6h0lIXdMBjkc0tp/Zg79ZzT52Biu320Jti5P8jNtpzRJjw= Received: from DESKTOP-S9E58SO.localdomain(mailfrom:cp0613@linux.alibaba.com fp:SMTPD_---0WysCTD4_1770640589 cluster:ay36) by smtp.aliyun-inc.com; Mon, 09 Feb 2026 20:36:34 +0800 From: cp0613@linux.alibaba.com To: atish.patra@linux.dev Cc: anup@brainfault.org, alex@ghiti.fr, pjw@kernel.org, guoren@kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drivers/perf: riscv: Keep the fixed counter counting Date: Mon, 9 Feb 2026 20:36:28 +0800 Message-ID: <20260209123628.1866-1-cp0613@linux.alibaba.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Wed, 4 Feb 2026 01:17:25 -0800, atish.patra@linux.dev wrote: > > The RISC-V SBI PMU driver disables all PMU counters during initialization > > via pmu_sbi_stop_all. For fixed counters CYCLE, TIME and INSTRET, this is > > unnecessary for the following two reasons: > > > > 1. Some kernel driver code may directly read CYCLE and INSTRET to perform > > simple performance analysis. > > Is this for some debugging purpose to read the instret/cycle count at > boot time or real use case for driver performance analysis ? > > If it is the latter, that will be problematic for various reasons such > as context switching will lead to inaccurate numbers. Hi Atish, Thanks for the reminder, but I might not be able to provide specific scenarios due to our niche usage. Therefore, let's just discuss the legacy usage of sysctl_perf_user_access. > > 2. In legacy mode, user space directly reads CYCLE and INSTRET. (echo 2 > > > /proc/sys/kernel/perf_user_access) > > > > Therefore, We keep counting CYCLE, TIME and INSTRET. > > > > Signed-off-by: Chen Pei > > --- > > drivers/perf/riscv_pmu_sbi.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > > index 7dd282da67ce..93aaab324443 100644 > > --- a/drivers/perf/riscv_pmu_sbi.c > > +++ b/drivers/perf/riscv_pmu_sbi.c > > @@ -899,6 +899,9 @@ static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) > > > > static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) > > { > > + /* We keep counting CYCLE, TIME and INSTRET. */ > > + pmu->cmask &= ~0x7; > > + > > This is incorrect. The cmask should be set based on the perf_user_access > value. We should not continue counting the CYCLE/INSTRET when legacy > mode is not set. if (sysctl_perf_user_access == SYSCTL_LEGACY) > csr_write(CSR_SCOUNTEREN, 0x7); else csr_write(CSR_SCOUNTEREN, 0x2); I have a slightly different understanding here. Regarding perf_user_access, I think it is only used to control user mode access permissions to CYCLE, TIME, and INSTRET (via SCOUNTEREN), but whether the counters themselves are in a counting state is another issue (via MCOUNTINHIBIT). I think the cmask in pmu_sbi_stop_all should represent a counter to stop the counting, rather than a permission configuration. The problem we are currently encountering is that even when switching to LEGACY mode, CYCLE and INSTRET are not counting, so we want to change this default behavior so that these three fixed counters are always in counting. Sorry for the late reply. I've reviewed some previous related discussions, and it seems that using time is more reasonable between cycle and time. However, for some small code snippets, there is a need to use cycle and instant (at least instant), so keeping them constantly counting doesn't seem to have any downsides. Thanks, Pei > > /* > > * No need to check the error because we are disabling all the counters > > * which may include counters that are not enabled yet.