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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8caf9ee8662sm1119957785a.37.2026.02.10.05.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Feb 2026 05:02:22 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vpnNl-00000003784-1qfn; Tue, 10 Feb 2026 09:02:21 -0400 Date: Tue, 10 Feb 2026 09:02:21 -0400 From: Jason Gunthorpe To: fangyu.yu@linux.alibaba.com Cc: tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, andrew.jones@oss.qualcomm.com, guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH 0/2] iommu/riscv: support range and non-leaf IOTLB invalidation Message-ID: <20260210130221.GE943673@ziepe.ca> References: <20260208144213.94856-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260208144213.94856-1-fangyu.yu@linux.alibaba.com> On Sun, Feb 08, 2026 at 10:42:11PM +0800, fangyu.yu@linux.alibaba.com wrote: > From: Fangyu Yu > > This series adds support for two RISC-V IOMMU v1.0.1 invalidation extensions in > the RISC-V IOMMU driver: > > - Address Range Invalidation (capabilities.S), which allows encoding a NAPOT > address range in the IOTINVAL.{VMA,GVMA} ADDR operand when the S bit is set, > reducing the number of invalidation commands for large or superpage-backed > mappings. > > - Non-leaf PTE Invalidation (capabilities.NL), which allows IOTINVAL.VMA with > AV=1 and NL=1 to invalidate cached non-leaf PTE information for the given > IOVA, addressing cases where updating mappings replaces a non-leaf entry. > > Patch 1 introduces the missing capability/operand definitions and switches the > IOTLB invalidation path to use NAPOT range invalidations when supported. > > Patch 2 adds the NL capability/operand definitions and extends the invalidation > path to optionally request non-leaf invalidation. When map_pages() replaces > non-leaf page-table entries, the driver invalidates the affected IOVA range with > non-leaf semantics. > > No functional changes are expected on hardware that does not advertise these > capabilities; the driver continues to fall back to the existing invalidation > behavior. > > Fangyu Yu (2): > iommu/riscv: Add NAPOT range invalidation support for IOTINVAL > iommu/riscv: Add non-leaf invalidation support These will need to be redone on top of the new page table code for riscv: https://patch.msgid.link/r/0-v3-9dbf0a72a51c+302-iommu_pt_riscv_jgg@nvidia.com It should get picked up early in the next cycle Jason