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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5mZ/lXvhkN7D+JuNblQtZbcpAbjZ0dZ8RdkUqwJbScph4lTbFY68keViO7AqJNiOB+fIbVgOvSxUWZR9Eja0vWXIuiZuhcUM0uBYwX5i6f4eVDpIpdn+hw+8Gilfty0PS2kDFzLKgKBu+g6vQby8qoye97tCKj4u+oS2iZZ7ApXO/Aqs5sXcv7D/16ArhcjL+VtU8O+ubJlHLwKioD5ZfvzdIf8DAjhlb7Wm/NXhs6bKILAtLO3Ac41Km7mIYeuQH00twG77yaW/W5JbLYn9Qghv4xI1uFR96HIp29UOHD7+sigfJLtZgsQAuhwQMnHHnepy21JJNC2NLMGhrGbWSSlDIJ96p4rz/ugDW4k8zJfZZiuH+M7QJXx7KThZHmnu9Lqn/Fxsc0YW66cOh/9TfsOr1E/5bz6A0T3+YJwGtlLPkrUDWabFn7KSglvAMPob X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2026 04:25:48.4125 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 604d4838-661f-415e-4b64-08de6d137600 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8027 Add support for new capabilities that will appear in future AMD CPUs: - Alternate disable bit with control only MSRs to eliminate the RMW race in existing IBS_{FETCH|OP}_CTL MSRs - RIP bit 63 filtering, which can be used as hardware assisted privilege filtering, enabling IBS for unprivileged users without software based privilege filtering - Fetch latency threshold filter to capture only high-latency fetch events - Streaming-store filter to sample only instructions that perform streaming stores - Remote socket indicator for load/store instructions Patches are prepared on tip/perf/core (7db06e329af3) + IBS fixes series IBS fixes series: https://lore.kernel.org/r/20260216042216.1440-1-ravi.bangoria@amd.com Perf tools patches: https://lore.kernel.org/r/20260119024328.897-1-ravi.bangoria@amd.com v1: https://lore.kernel.org/r/20260116033450.965-1-ravi.bangoria@amd.com v1->v2: - Split fixes series from future enhancements - Replace magic numbers with macros Ravi Bangoria (7): perf/amd/ibs: Define macro for ldlat mask and shift perf/amd/ibs: Add new MSRs and CPUID bits definitions perf/amd/ibs: Support IBS_{FETCH|OP}_CTL2[Dis] to eliminate RMW race perf/amd/ibs: Enable fetch latency filtering perf/amd/ibs: Enable RIP bit63 hardware filtering perf/amd/ibs: Enable streaming store filter perf/amd/ibs: Advertise remote socket capability arch/x86/events/amd/ibs.c | 238 ++++++++++++++++++++++++++++-- arch/x86/include/asm/amd/ibs.h | 4 +- arch/x86/include/asm/msr-index.h | 2 + arch/x86/include/asm/perf_event.h | 55 ++++--- 4 files changed, 266 insertions(+), 33 deletions(-) -- 2.43.0