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Wed, 18 Feb 2026 00:12:50 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ad1a9d624esm118123685ad.49.2026.02.18.00.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Feb 2026 00:12:50 -0800 (PST) From: Krishna Chaitanya Chundru Date: Wed, 18 Feb 2026 13:42:25 +0530 Subject: [PATCH v7 3/3] PCI: Add support for PCIe WAKE# interrupt Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260218-wakeirq_support-v7-3-0d4689830207@oss.qualcomm.com> References: <20260218-wakeirq_support-v7-0-0d4689830207@oss.qualcomm.com> In-Reply-To: <20260218-wakeirq_support-v7-0-0d4689830207@oss.qualcomm.com> To: "Rafael J. Wysocki" , Len Brown , Pavel Machek , Greg Kroah-Hartman , Danilo Krummrich , Bjorn Helgaas , Bartosz Golaszewski , Linus Walleij , Bartosz Golaszewski , Linus Walleij Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, sherry.sun@nxp.com, driver-core@lists.linux.dev, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1771402347; l=7967; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=YyvIpWrTFLi6XlA78epLgR4oDc+qO1nmiVhSzx9chWw=; b=T9yc43Z0e8+NjXJSIlHu3tdFO6HaY32cKsWHdKZZ2VqhHBCDBrlY90crKCb6DxcOXTnxOfSLF 9SUKBwO4bV5D1Zrj1R2rRIXSVgYARNPyuZm3lMN/9oxEZq/mzzo65Bk X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: JzB3dH6rdboQmEm30DxZwAV-fiDaYAKE X-Proofpoint-ORIG-GUID: JzB3dH6rdboQmEm30DxZwAV-fiDaYAKE X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjE4MDA3MSBTYWx0ZWRfX+vTDtoZxzerQ rdf4NqQYJWjDqVzJyA9KsIy9C4mHBAF9cYrO7h4gS8aa8Ff5r4r0LEFtTNApvDD+kbb1bFgtojx kgvpCAdmEE1yeYVR1NvaOWBf+gAZldqfeT/INcDzzk+BkjgFpwEi9yqhmSXKGPiFox2iBCM7N5E 5pdcZVX1Ejk/VhJrA6cFPypYtG76lsJFh7xrdh7FnvUUg9gav3SOyD6DlZhYlh+eG7X0NQMOWSy u7AWWW5BMrGf1fSb+OpLV5xY/VjpxUPu37mE4UUMK/8iEm3BwEfIPPwNP6nxv5v7DMAJfU4ldw3 Nw+4+nHpNCnFAGpBARIyGlj+tByZ7OSFU9aKWKLTQhXacUJisuZ/sEREYcTFY0xJMIEBUnNteiI x/iuKiLzBHxR1RO/P3iOavNHB8LJrf7X2DLAfPSCefxoC8diofw+ybyk2is0m8qo9b26JwNFA8V rPduYsyWB4AoFcymcYw== X-Authority-Analysis: v=2.4 cv=Q8rfIo2a c=1 sm=1 tr=0 ts=69957484 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=NEAV23lmAAAA:8 a=KKAkSRfTAAAA:8 a=ttF918e8ocTVMR-R1j4A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-17_04,2026-02-16_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 clxscore=1015 bulkscore=0 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602180071 According to the PCI Express specification (PCIe r7.0, Section 5.3.3.2), two link wakeup mechanisms are defined: Beacon and WAKE#. Beacon is a hardware-only mechanism and is invisible to software (PCIe r7.0, Section 4.2.7.8.1). This change adds support for the WAKE# mechanism in the PCI core. According to the PCIe specification, multiple WAKE# signals can exist in a system or each component in the hierarchy could share a single WAKE# signal. In configurations involving a PCIe switch, each downstream port (DSP) of the switch may be connected to a separate WAKE# line, allowing each endpoint to signal WAKE# independently. From figure 5.4 in sec 5.3.3.2, WAKE# can also be terminated at the switch itself. To support this, the WAKE# should be described in the device tree node of the endpoint/bridge. If all endpoints share a single WAKE# line, then each endpoint node should describe the same WAKE# signal or a single WAKE# in the Root Port node. In pci_device_add(), PCI framework will search for the WAKE# in device node, If not found, it searches in its upstream port only if upstream port is Root Port. Once found, register for the wake IRQ in shared mode, as the WAKE# may be shared among multiple endpoints. When a device asserts WAKE#, PM core will wakeup the system, resume the device and its parent(s) in the hierarchy, which will cause the restoration of power and refclk to the device. WAKE# is added in dts schema and merged based on below links. Link: https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@oss.qualcomm.com/ Link: https://github.com/devicetree-org/dt-schema/pull/170 Reviewed-by: Linus Walleij Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/of.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.c | 9 +++++++++ drivers/pci/pci.h | 8 ++++++++ drivers/pci/probe.c | 2 ++ drivers/pci/remove.c | 1 + include/linux/pci.h | 2 ++ 6 files changed, 77 insertions(+) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 9bb5f258759be3f1e23496f083353600a4ef6743..23248900253faafaf9509d87c531b454fca41798 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) "PCI: OF: " fmt #include +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include "pci.h" #ifdef CONFIG_PCI @@ -586,6 +588,59 @@ int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) return irq_create_of_mapping(&oirq); } EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci); + +static void pci_configure_wake_irq(struct pci_dev *pdev, struct gpio_desc *wake) +{ + int ret, wake_irq; + + wake_irq = gpiod_to_irq(wake); + if (wake_irq < 0) { + pci_err(pdev, "Failed to get wake irq: %d\n", wake_irq); + return; + } + + device_init_wakeup(&pdev->dev, true); + + ret = dev_pm_set_dedicated_shared_wake_irq(&pdev->dev, wake_irq, + IRQ_TYPE_EDGE_FALLING); + if (ret < 0) { + pci_err(pdev, "Failed to set wake IRQ: %d\n", ret); + device_init_wakeup(&pdev->dev, false); + } +} + +void pci_configure_of_wake_gpio(struct pci_dev *dev) +{ + struct device_node *dn = pci_device_to_OF_node(dev); + struct pci_dev *upstream; + struct gpio_desc *gpio; + + if (!dn) + return; + + gpio = fwnode_gpiod_get(of_fwnode_handle(dn), "wake", + GPIOD_IN | GPIOD_FLAGS_BIT_NONEXCLUSIVE, NULL); + if (IS_ERR(gpio)) { + /* + * In case the entire topology shares a single WAKE# signal, look for it + * in the upstream bridge node. But if it is not Root Port, then skip it. + */ + upstream = pci_upstream_bridge(dev); + if (upstream && pci_is_root_bus(upstream->bus) && upstream->wake) + pci_configure_wake_irq(dev, upstream->wake); + } else { + dev->wake = gpio; + pci_configure_wake_irq(dev, gpio); + } +} + +void pci_remove_of_wake_gpio(struct pci_dev *dev) +{ + dev_pm_clear_wake_irq(&dev->dev); + device_init_wakeup(&dev->dev, false); + gpiod_put(dev->wake); + dev->wake = NULL; +} #endif /* CONFIG_OF_IRQ */ static int pci_parse_request_of_pci_ranges(struct device *dev, diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index f3244630bfd05b15d52f866d80a015ed21f98f49..225cb861b3425700fc0d9d4805f5d9efcaab6f56 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1123,6 +1123,15 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev) return acpi_pci_bridge_d3(dev); } +void platform_pci_configure_wake(struct pci_dev *dev) +{ + return pci_configure_of_wake_gpio(dev); +} + +void platform_pci_remove_wake(struct pci_dev *dev) +{ + return pci_remove_of_wake_gpio(dev); +} /** * pci_update_current_state - Read power state of given device and cache it * @dev: PCI device to handle. diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 13d998fbacce6698514d92500dfea03cc562cdc2..22709573e41caf0ed45b20ee7ded5963f55aa9fe 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -282,6 +282,8 @@ void pci_msix_init(struct pci_dev *dev); bool pci_bridge_d3_possible(struct pci_dev *dev); void pci_bridge_d3_update(struct pci_dev *dev); int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); +void platform_pci_configure_wake(struct pci_dev *dev); +void platform_pci_remove_wake(struct pci_dev *dev); static inline bool pci_bus_rrs_vendor_id(u32 l) { @@ -1195,6 +1197,9 @@ void pci_release_of_node(struct pci_dev *dev); void pci_set_bus_of_node(struct pci_bus *bus); void pci_release_bus_of_node(struct pci_bus *bus); +void pci_configure_of_wake_gpio(struct pci_dev *dev); +void pci_remove_of_wake_gpio(struct pci_dev *dev); + int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); bool of_pci_supply_present(struct device_node *np); int of_pci_get_equalization_presets(struct device *dev, @@ -1240,6 +1245,9 @@ static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_br return 0; } +static inline void pci_configure_of_wake_gpio(struct pci_dev *dev) { } +static inline void pci_remove_of_wake_gpio(struct pci_dev *dev) { } + static inline bool of_pci_supply_present(struct device_node *np) { return false; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2975974f35e88b5025701d2b721df8386419de8d..7f5132c0c8de36a6ec2775468a3d4e5156a046d0 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2771,6 +2771,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) /* Establish pdev->tsm for newly added (e.g. new SR-IOV VFs) */ pci_tsm_init(dev); + platform_pci_configure_wake(dev); + pci_npem_create(dev); pci_doe_sysfs_init(dev); diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index e9d519993853f92f1810d3eff9f44ca7e3e1abd9..d781b41e57c4444077075690cec926a9fe15334f 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -35,6 +35,7 @@ static void pci_destroy_dev(struct pci_dev *dev) if (pci_dev_test_and_set_removed(dev)) return; + platform_pci_remove_wake(dev); pci_doe_sysfs_teardown(dev); pci_npem_remove(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 1c270f1d512301de4d462fe7e5097c32af5c6f8d..d1e08df8a8deaa87780589f23242767fdcdba541 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -586,6 +586,8 @@ struct pci_dev { /* These methods index pci_reset_fn_methods[] */ u8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */ + struct gpio_desc *wake; /* Holds WAKE# gpio */ + #ifdef CONFIG_PCIE_TPH u16 tph_cap; /* TPH capability offset */ u8 tph_mode; /* TPH mode */ -- 2.34.1