From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2613234C83C for ; Thu, 19 Feb 2026 16:52:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.92.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771519969; cv=none; b=fyaRDqyxmqVF9LpACcDAm3tEZJXS/9AwT+BfH4+mfacmLwUaPddt7Ior/0KRSr7du9fMrfZNS2RV9sjkzEZviAKqe8K3F+5K05TfgBZ/iXIe9LpXYYvrfIz+/JkG9C9ohmUVJRMKQapnyneaQ+82e5Vm195tPZ/OZ+HkQBiIx+E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771519969; c=relaxed/simple; bh=jzThauPRhQQewb1HN2K6jXEZcq3tBpmT8RNQdybai04=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bE1AR0/dQILMBKzczjjs/xgODyEnrPdnDyEqA19g0PM/V8ucWhmjY8x20SRmk9Yimk3Z8/RO+JN28X0m7Zk/TK56vIBUYJ0qs5kp0yo5qZDwmdEsg9aDj/oFdIOvyDc0+hnXkPDc1kbx9HyYUaBJsKTBR4p6/fOWUMzBCe2tttQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org; spf=none smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=rEmt2M+K; arc=none smtp.client-ip=90.155.92.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="rEmt2M+K" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=LZNw0tKx6s6fXG7fEAEW/vaoxU+B09U0WqJZkzw0ZbU=; b=rEmt2M+K5a4Z4hu7VlF2+Z/H7/ U+x6wvj9d8BmwloszC0+IHDvMNE4ZcHCPtBNmY/DYsnqaHhB/v6scNekk6Jt8zPaMXvNkP4OnoGvj 0sUVuK6eWjeoKakFtHiG7m/EOR5zG4CAyxTqQA+jX6w33t8Iexx4URn7B2jtveXjvn+6LAm42QhaY nAmYrp7MdSjpvQXm89gXZ1YTeazlI0uEo7Y91v9OKG2ghZ/2eMhjB8ec87OrTpAoBYPz3L9i/VaJO dT/u7f1OAIKwJdcOkP3fAbKETbk2fAl3I8aCT5jrWquzR81nNssvMGbM/LEEJ+oGu/zr4BxsPqRnF xyZfp3NQ==; Received: from 77-249-17-252.cable.dynamic.v4.ziggo.nl ([77.249.17.252] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.98.2 #2 (Red Hat Linux)) id 1vt7GH-00000001Zkk-3IAw; Thu, 19 Feb 2026 16:52:22 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 3F98D3004AB; Thu, 19 Feb 2026 17:52:21 +0100 (CET) Date: Thu, 19 Feb 2026 17:52:21 +0100 From: Peter Zijlstra To: Madadi Vineeth Reddy Cc: Tim Chen , Ingo Molnar , K Prateek Nayak , "Gautham R . Shenoy" , Vincent Guittot , Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 15/21] sched/cache: Disable cache aware scheduling for processes with high thread counts Message-ID: <20260219165221.GM1395266@noisy.programming.kicks-ass.net> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Feb 18, 2026 at 11:24:05PM +0530, Madadi Vineeth Reddy wrote: > > diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c > > index d1145997b88d..86b6b08e7e1e 100644 > > --- a/kernel/sched/fair.c > > +++ b/kernel/sched/fair.c > > @@ -1223,6 +1223,19 @@ static inline bool valid_llc_buf(struct sched_domain *sd, > > return valid_llc_id(id); > > } > > > > +static bool exceed_llc_nr(struct mm_struct *mm, int cpu) > > +{ > > + int smt_nr = 1; > > + > > +#ifdef CONFIG_SCHED_SMT > > + if (sched_smt_active()) > > + smt_nr = cpumask_weight(cpu_smt_mask(cpu)); > > +#endif > > + > > + return !fits_capacity((mm->sc_stat.nr_running_avg * smt_nr), > > + per_cpu(sd_llc_size, cpu)); > > > On Power10/Power11 with SMT4 and LLC size of 4, this check > effectively disables cache-aware scheduling for any process. > > I raised this point in v1 as well. Increasing the threshold > doesn't seem like a viable solution either, as that would regress > hackbench/ebizzy. > > Is there a way to make this useful for architectures with small LLC > sizes? One possible approach we were exploring is to have LLC at a > hemisphere level that comprise multiple SMT4 cores. One way forward would be to use a llc-mask instead of a single llc value for preference. I think this got mentioned before, and I think it makes sense to do this later. But once you can have a 'few' LLCs as preference, this constraint becomes a little easier.