From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B983B1E8826 for ; Mon, 23 Feb 2026 10:20:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771842030; cv=none; b=CyQqxmciKOP7B1qm4vT8HbwdiadbMm0W6P9st3v2OH1PFeclB4nuo/0yT+s1W/2Ci+1FG1ANTGzOEh4+hrt2tdZxHFV6rDwdQ4Tf7NjpBUlQnDamN4/5+On0LFuix0HDXCr2Ne8pFGICTX5qaUnB53CCV0pVNrm8QcYH6QtP5RE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771842030; c=relaxed/simple; bh=fxh20OoRIDIJw2Z8F3GMbn8xf8EQoWg+ERVhvDDIVg8=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=C6tIIsXbyLFVVDI6LWc5XmGoVLIXP8jhUJ3/O0TSkf8TrcWUgbJ/yK5iP9tX+0cO291F0CRS7sbQ9sC8LLnUsqS8NW0JwNJI0+3KmLP1QzbNgHq5ipaNC5I7/Oq/G4qz7pAhXUdF8t/dkIdHs1lgIAHicj1UaNAW/2UL7OzjiDA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=vkq/ZuMC; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="vkq/ZuMC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1771842029; x=1803378029; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=fxh20OoRIDIJw2Z8F3GMbn8xf8EQoWg+ERVhvDDIVg8=; b=vkq/ZuMCjxvJiOaqYnFA5ENiZgjr33FwZsrgG/mrhSsR5MWjALH4cFKu jj2JtczR+vhvAnKqVfo+3cwi0va2DJq3j7ExvRPfqIEA6coo+DHD96kfq 7AVVH6wXQNhSO6Df31wCMhC5vrhIuOmb6m2KZMTr11WgfTN6Cpdldkz6T 2oke+r1qfsehquZlp5SbGlOLkjs3ntb0syYeCIKO6xUgP9kfkidmAUwbZ Eka3UaxNUhgmAv3/oqDsM3QemNtKA39kndmCE1ye/KYZs+rAG87QCsLma zvdjqI8MlgueBfTGq+G0/Rwv6ilOsxc3S+iEq0wDJQ+A2ORsGVdWOxLZ1 Q==; X-CSE-ConnectionGUID: xLxJrVz4SA+TZ2kb8t2UqQ== X-CSE-MsgGUID: VwZNW30OScC7E8KufsFKmw== X-IronPort-AV: E=Sophos;i="6.21,306,1763449200"; d="scan'208";a="220994669" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2026 03:20:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Mon, 23 Feb 2026 03:19:48 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 23 Feb 2026 03:19:43 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , CC: Subject: [PATCH v3 0/4] Add LVDS display support and PLL handling Date: Mon, 23 Feb 2026 15:49:16 +0530 Message-ID: <20260223101920.284697-1-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="y" Content-Transfer-Encoding: 8bit Hi all, This patch series adds LVDS display support for the Atmel HLCDC driver and introduces ATMEL_XLCDC_CLKBYP flags and proper handling of the LVDS PLL clock required for such panels. The Atmel XLCDC IP supports multiple output types — Parallel RGB, MIPI DSI, and LVDS. While the existing implementation handles RGB and MIPI displays using the LCD generic clock (sys_clk), LVDS panels require the dedicated LVDS PLL clock (lvds_pll_clk).Configuring the LVDS PLL clock rate automatically based on the panel pixel clock, eliminates the need for assigned-clock-rates entries in the device tree Change logs are mentioned in individual patches Dharma Balasubiramani (1): drm: atmel-hlcdc: configure LVDS PLL clock rate for LVDS Displays Manikandan Muralidharan (3): mfd: atmel-hlcdc: fetch LVDS PLL clock for LVDS display drm: atmel-hlcdc: bypass clock divider for LVDS displays drm: atmel-hlcdc: add support for LVDS output formats .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 139 +++++++++++++----- drivers/mfd/atmel-hlcdc.c | 13 +- include/linux/mfd/atmel-hlcdc.h | 2 + 3 files changed, 118 insertions(+), 36 deletions(-) -- 2.25.1