From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D4961C84A2 for ; Mon, 23 Feb 2026 10:20:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771842021; cv=none; b=UWDnOlz2Zc6fXtVPgMYbwQjqn6qzzaqU6Wzdx00ByDchgilc3BgR6uA8qCRmpOnhok04Ww/EsMTL+U336m+UFzpSyx8PBDb0Bw7wBm1mYMatVk8muPb66URTNJo2Ays2trOmciqnKbI47v/nMQ2dWM6j+XnmuHyivH4fmYtWFUM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771842021; c=relaxed/simple; bh=HYWBr38iHIjb+NSx2zGe9SgBNR2/Jd2Z4h5rS9bUVNw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=C1MNnqIefNUTbr2V3MdaICHvmUR0ZwSQeXYWc1BPZYe3qjw6nrdpbhvX4zpo9Xlt1kksZ8a0PVYVph20jcPEhwogmM+71hHiE5tFadQ2V7b4gR7ghQ1+d9OlXXbU9/jVdqbntSUQnAYHHn9BYWdy/npmzbY6ag3DYk7bLmOHZp4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=FV2H6XpG; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="FV2H6XpG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1771842020; x=1803378020; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HYWBr38iHIjb+NSx2zGe9SgBNR2/Jd2Z4h5rS9bUVNw=; b=FV2H6XpGXHmQzzfK0t8tbZFa6L94DIptGtqD5ntvN9BZkSt0bZdI/1jA dzzBPDOdSiVU11pxcEitkAh/NRLQLE2SE+3p8auQT5Wu4mSjpR9A25S5X W2dv4naTiYh/jDnBxyPtM8MB+zz2yzalIRiCrEdj/RESr1dwzNkTUn0gD xyVSybzIgXjT4ej8dgHjDa4ylqw9C7Bhz9AqXZBSBR2g9006M96GDUfkw f59lGyAQXC5nlhUha7CeVvjZ8rSrbhdVJ5uXrOfzY39ppdOFPYwlOdWEv +nDmf2rcJVN2t1dFg6JJapS2Sm+3HiXs2stSzxlS6vzfEQfthexdmQ3b3 g==; X-CSE-ConnectionGUID: Pkelvpk5TzC1b4CVtpcYwQ== X-CSE-MsgGUID: v51EDN1ETbOmCom1RI3NQw== X-IronPort-AV: E=Sophos;i="6.21,306,1763449200"; d="scan'208";a="220994658" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2026 03:20:14 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 23 Feb 2026 03:19:54 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 23 Feb 2026 03:19:49 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , CC: , Dharma Balasubiramani Subject: [PATCH v3 1/4] mfd: atmel-hlcdc: fetch LVDS PLL clock for LVDS display Date: Mon, 23 Feb 2026 15:49:17 +0530 Message-ID: <20260223101920.284697-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260223101920.284697-1-manikandan.m@microchip.com> References: <20260223101920.284697-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain The XLCDC IP supports parallel RGB, MIPI DSI and LVDS Display. The LCD Generic clock (sys_clk) is used for Parallel RGB and MIPI displays, while the LVDS PLL clock (lvds_pll_clk) is used for LVDS displays.Since both the clocks cannot co-exist together in the DT for a given display, this patch tries sys_clk first (RGB/MIPI), fallback to lvds_pll_clk (LVDS). Signed-off-by: Manikandan Muralidharan Signed-off-by: Dharma Balasubiramani --- changes in v3: - Rephrase the comments, err logs. - assign NULL to sys_clk to avoid Oops error when referenced in pwm-atmel-hlcdc.c changes in v2: - Rephrase the comments, commit message and err logs - Replace dev_err wwith dev_warn - Remove Initializing sys_clk and lvds_pll_clk to NULL post devm_kzalloc() call --- drivers/mfd/atmel-hlcdc.c | 13 +++++++++++-- include/linux/mfd/atmel-hlcdc.h | 1 + 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/atmel-hlcdc.c b/drivers/mfd/atmel-hlcdc.c index 4c4e35d404f3..0f83ad7ba15c 100644 --- a/drivers/mfd/atmel-hlcdc.c +++ b/drivers/mfd/atmel-hlcdc.c @@ -108,10 +108,19 @@ static int atmel_hlcdc_probe(struct platform_device *pdev) return PTR_ERR(hlcdc->periph_clk); } + /* + * Retrieve one of the primary clocks required for LCD operation: + * prefer sys_clk (for RGB/MIPI), and + * fall back to lvds_pll_clk (for LVDS) if needed. + */ hlcdc->sys_clk = devm_clk_get(dev, "sys_clk"); if (IS_ERR(hlcdc->sys_clk)) { - dev_err(dev, "failed to get system clock\n"); - return PTR_ERR(hlcdc->sys_clk); + hlcdc->sys_clk = NULL; + hlcdc->lvds_pll_clk = devm_clk_get(dev, "lvds_pll_clk"); + if (IS_ERR(hlcdc->lvds_pll_clk)) { + dev_err(dev, "Failed to obtain both the LCDC (generic) and LVDS PLL clocks\n"); + return PTR_ERR(hlcdc->lvds_pll_clk); + } } hlcdc->slow_clk = devm_clk_get(dev, "slow_clk"); diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcdc.h index 80d675a03b39..07c2081867fd 100644 --- a/include/linux/mfd/atmel-hlcdc.h +++ b/include/linux/mfd/atmel-hlcdc.h @@ -75,6 +75,7 @@ */ struct atmel_hlcdc { struct regmap *regmap; + struct clk *lvds_pll_clk; struct clk *periph_clk; struct clk *sys_clk; struct clk *slow_clk; -- 2.25.1