From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AE25356A3E for ; Mon, 23 Feb 2026 10:20:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771842032; cv=none; b=QRyd7ZCXSFXCGoOFToliOUHm2perLQenKfgPRiR58ELrOv6WZmxqmmHV2AmXD6oJfnCzzo/kzam/qaBVQ/BVqf1RquHI6K8VTs604VZ6bzwpb3KdDD9v2NkHH9qhPbvWF4i+fRb7q6JA0VcHYXTRZ3EAIaeI2myFQcfb2OLwSJo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771842032; c=relaxed/simple; bh=XGUvf+KenQzk8k4vozQBvoxGs/tTB8x65xysSNH3uRc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Wtsa9Dhwk1gPYmiRajHlDeRq/3H3b3If3atcf2EKLRr7VDPEQMt2DN9dBpg87jIfFRKpoP9S8kyOsoaRQNLoEZtLyyDGwyd7GXDz88PwIAF/A0MwAa2GhevfzlbZjLzDXki6OWfimfLxSK8E0txuKMKtBxJxPuJ+8SvP7IsIxYo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=2o7vaE95; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="2o7vaE95" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1771842030; x=1803378030; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XGUvf+KenQzk8k4vozQBvoxGs/tTB8x65xysSNH3uRc=; b=2o7vaE95ZqUMIbez3UrvXpMPRVpd5yOfBaUtGNXr2Bkj8Uqv4OiOsJeO h/k4wvkhmRcfnX0CZd2K0THz79uY8nQ8izFbHlhQyPemG4pWYwH8Fz9qX UbW092Zw+HBv7wl0hsn74rYSqt2ym7NBnUfH/yB67A2ifQ6MzKfAfaNp9 uOUyPyJpa0cOFoU2DOGP5RDl7Jr4n0wxvZAKJ7ohXVACaKiPZvrMZcaw8 HGKX2gi3JY2XWImfkGihR4qTOChf2Sf5ICwLzfRudRnAOPkla9IRIMHV6 q0amIi18cdEZH6gqKI51A0W8+8hxP6OtCC1TiX0J10awL1rFQuh6iFit3 g==; X-CSE-ConnectionGUID: xLxJrVz4SA+TZ2kb8t2UqQ== X-CSE-MsgGUID: d6Eg9STLReWgxqckjEf6tw== X-IronPort-AV: E=Sophos;i="6.21,306,1763449200"; d="scan'208";a="220994672" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2026 03:20:29 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.87.151) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Mon, 23 Feb 2026 03:20:00 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 23 Feb 2026 03:19:54 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , CC: , Dharma Balasubiramani Subject: [PATCH v3 2/4] drm: atmel-hlcdc: configure LVDS PLL clock rate for LVDS Displays Date: Mon, 23 Feb 2026 15:49:18 +0530 Message-ID: <20260223101920.284697-3-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260223101920.284697-1-manikandan.m@microchip.com> References: <20260223101920.284697-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Dharma Balasubiramani As per datasheet, The LVDS PLL clock runs at 7 times the panel pixel clock. Set the LVDS PLL clock to eliminate the need of assiging them in the DT and fallback to sys_clk for non-LVDS displays with proper error handling. Signed-off-by: Dharma Balasubiramani Signed-off-by: Manikandan Muralidharan --- Changes in v3: - Rephrase commit message and comment block Changes in v2: - Rephrase commit message and comment block --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 36 ++++++++++++++++--- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index b075f291847f..26c9fbdfd871 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -100,7 +100,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) drm_connector_list_iter_end(&iter); } - ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + if (crtc->dc->hlcdc->lvds_pll_clk) + ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk); + else + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); if (ret) return; @@ -187,7 +190,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) ATMEL_XLCDC_DPI : ATMEL_HLCDC_MODE_MASK), cfg); - clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + if (crtc->dc->hlcdc->lvds_pll_clk) + clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk); + else + clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); } static enum drm_mode_status @@ -243,7 +249,11 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, 10, 1000)) drm_warn(dev, "Atmel LCDC status register CLKSTS timeout\n"); - clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + if (crtc->dc->hlcdc->lvds_pll_clk) + clk_disable_unprepare(crtc->dc->hlcdc->lvds_pll_clk); + else + clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); + pinctrl_pm_select_sleep_state(dev->dev); pm_runtime_allow(dev->dev); @@ -256,15 +266,33 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, { struct drm_device *dev = c->dev; struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); + struct drm_display_mode *adj = &c->state->adjusted_mode; struct regmap *regmap = crtc->dc->hlcdc->regmap; unsigned int status; + int ret; pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); pinctrl_pm_select_default_state(dev->dev); - clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + + /* + * Set LVDS PLL clock rate (7x pixel clock) if available + */ + if (crtc->dc->hlcdc->lvds_pll_clk) { + ret = clk_set_rate(crtc->dc->hlcdc->lvds_pll_clk, + (adj->clock * 7000)); + if (ret) { + drm_err(dev, "Failed to set LVDS PLL clk rate: %d\n", ret); + return; + } + ret = clk_prepare_enable(crtc->dc->hlcdc->lvds_pll_clk); + } else { + ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk); + } + if (ret) + return; regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK); if (regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, -- 2.25.1