From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D94FA1E8826 for ; Mon, 23 Feb 2026 10:20:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771842023; cv=none; b=Sb2pUkQzyVmi3Dgc3dV+H0YMmYmVrVJZPU8UVR9fMOemkkEzLN3O+iD8qSQnejL4oAShwgLfGclAcCfh05LbZmgCGbRgd5d9zglXITcgrxRdEE1CFPfgVy0IJyvSgy7/EkoE3My55WDEWP2/eZKz/3amq+EpS5fkISM+lwFROJg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771842023; c=relaxed/simple; bh=SlO0Q8vJ+yci4yGpTaLDlVlevoqk4pzFvMHvGyAYDTE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NCHYbCjAvKwji0Os0s947+JSV0VTxqUq8EPKjonKjnnezw9o7v6K7yFNOmF3Xlb4ZvAapm98+yu7wubkk7+l2usuTqTR9yu+7ugQTVjELo540kXVTDff1utJcnfCil/Q0SFasxjb0S7XxZdkELRDenTltTs5XXACBOK2m9jNT5Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=eKwSivKY; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="eKwSivKY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1771842021; x=1803378021; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=SlO0Q8vJ+yci4yGpTaLDlVlevoqk4pzFvMHvGyAYDTE=; b=eKwSivKY7Im/hVru4tAdFwvcgwwmVzv0I+eadSOnE0noPbLLoq8O2BIz 7cPd+tn2CW7w2w+VwSSAchyaD09Zp2+vKJXXdBtRjbBzfgG0nsbWutk1o WlSCLWVp6y86LLPSVNB62kr5dUM1rA3UyfSM6Ms0yTvrk2KaseitMIam9 QXSK9k7T7eL7htShRQWCRjQZfC9z9m3NxRDds19UczBJdHDqYL0JRG7BK TLM7N747Moc8qpdNhojLqeJ1oIjqwe4GJB4Pen3h+TE70qiBSj/c7P813 mEGnszem/kXOcbKAOf+Lp2G6/yOkQDJXdVHF+8JL/EPd+wa38wYZ8+Y5G A==; X-CSE-ConnectionGUID: dKUGnVN8SY6a+wGmQv7obw== X-CSE-MsgGUID: By9YC4OeSqy+Ol2Ny+ULhg== X-IronPort-AV: E=Sophos;i="6.21,306,1763449200"; d="scan'208";a="220994662" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Feb 2026 03:20:18 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Mon, 23 Feb 2026 03:20:04 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Mon, 23 Feb 2026 03:20:00 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , CC: Subject: [PATCH v3 3/4] drm: atmel-hlcdc: bypass clock divider for LVDS displays Date: Mon, 23 Feb 2026 15:49:19 +0530 Message-ID: <20260223101920.284697-4-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260223101920.284697-1-manikandan.m@microchip.com> References: <20260223101920.284697-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain For LVDS displays with pre-configured PLL clock, bypass the clock divider calculation by setting ATMEL_XLCDC_CLKBYP flag. For non-LVDS displays, retain existing clock divider calculation logic to determine appropriate clock scaling based on display requirements. Signed-off-by: Manikandan Muralidharan --- changes in v3: - Introduce ATMEL_XLCDC_CLKBYP to this series --- .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 65 ++++++++++--------- include/linux/mfd/atmel-hlcdc.h | 1 + 2 files changed, 36 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 26c9fbdfd871..73ac5ebbe121 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -127,39 +127,44 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) (adj->crtc_hdisplay - 1) | ((adj->crtc_vdisplay - 1) << 16)); - prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); - mode_rate = adj->crtc_clock * 1000; - if (!crtc->dc->desc->fixed_clksrc) { - prate *= 2; - cfg |= ATMEL_HLCDC_CLKSEL; - mask |= ATMEL_HLCDC_CLKSEL; - } + if (crtc->dc->hlcdc->lvds_pll_clk) { + cfg |= ATMEL_XLCDC_CLKBYP; + mask |= ATMEL_XLCDC_CLKBYP; + } else { + prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); + mode_rate = adj->crtc_clock * 1000; + if (!crtc->dc->desc->fixed_clksrc) { + prate *= 2; + cfg |= ATMEL_HLCDC_CLKSEL; + mask |= ATMEL_HLCDC_CLKSEL; + } - div = DIV_ROUND_UP(prate, mode_rate); - if (div < 2) { - div = 2; - } else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) { - /* The divider ended up too big, try a lower base rate. */ - cfg &= ~ATMEL_HLCDC_CLKSEL; - prate /= 2; div = DIV_ROUND_UP(prate, mode_rate); - if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) - div = ATMEL_HLCDC_CLKDIV_MASK; - } else { - int div_low = prate / mode_rate; - - if (div_low >= 2 && - (10 * (prate / div_low - mode_rate) < - (mode_rate - prate / div))) - /* - * At least 10 times better when using a higher - * frequency than requested, instead of a lower. - * So, go with that. - */ - div = div_low; - } + if (div < 2) { + div = 2; + } else if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) { + /* The divider ended up too big, try a lower base rate. */ + cfg &= ~ATMEL_HLCDC_CLKSEL; + prate /= 2; + div = DIV_ROUND_UP(prate, mode_rate); + if (ATMEL_HLCDC_CLKDIV(div) & ~ATMEL_HLCDC_CLKDIV_MASK) + div = ATMEL_HLCDC_CLKDIV_MASK; + } else { + int div_low = prate / mode_rate; + + if (div_low >= 2 && + (10 * (prate / div_low - mode_rate) < + (mode_rate - prate / div))) + /* + * At least 10 times better when using a higher + * frequency than requested, instead of a lower. + * So, go with that. + */ + div = div_low; + } - cfg |= ATMEL_HLCDC_CLKDIV(div); + cfg |= ATMEL_HLCDC_CLKDIV(div); + } if (connector && connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcdc.h index 07c2081867fd..19504d3ea12c 100644 --- a/include/linux/mfd/atmel-hlcdc.h +++ b/include/linux/mfd/atmel-hlcdc.h @@ -44,6 +44,7 @@ #define ATMEL_XLCDC_HEO_UPDATE BIT(3) #define ATMEL_HLCDC_CLKPOL BIT(0) +#define ATMEL_XLCDC_CLKBYP BIT(1) #define ATMEL_HLCDC_CLKSEL BIT(2) #define ATMEL_HLCDC_CLKPWMSEL BIT(3) #define ATMEL_HLCDC_CGDIS(i) BIT(8 + (i)) -- 2.25.1