From: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
To: rafael@kernel.org, daniel.lezcano@linaro.org
Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Subject: [PATCH] thermal: intel: int340x: Read DDR data rate for Nova Lake
Date: Mon, 23 Feb 2026 11:04:20 -0800 [thread overview]
Message-ID: <20260223190420.874853-1-srinivas.pandruvada@linux.intel.com> (raw)
Add support for reading DDR data rate from PCI config offset.
The register details are:
CFG Offset : 0xE0
Bits : 11:2
DDR Data rate is in 33.33 MTPS units.
Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
---
.../int340x_thermal/processor_thermal_rfim.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c b/drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c
index 314fbc1f490f..2e834a175471 100644
--- a/drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c
+++ b/drivers/thermal/intel/int340x_thermal/processor_thermal_rfim.c
@@ -402,6 +402,11 @@ static ssize_t rfi_restriction_show(struct device *dev,
return sysfs_emit(buf, "%llu\n", resp);
}
+ /* ddr_data_rate */
+static const struct mmio_reg nvl_ddr_data_rate_reg = { 1, 0xE0, 10, 0x3FF, 2};
+
+static const struct mmio_reg *ddr_data_rate_reg;
+
static ssize_t ddr_data_rate_show(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -410,10 +415,20 @@ static ssize_t ddr_data_rate_show(struct device *dev,
u64 resp;
int ret;
+ if (ddr_data_rate_reg) {
+ u16 reg_val;
+
+ pci_read_config_word(to_pci_dev(dev), ddr_data_rate_reg->offset, ®_val);
+ resp = (reg_val >> ddr_data_rate_reg->shift) & ddr_data_rate_reg->mask;
+ resp = (resp * 3333) / 100;
+ goto ret_resp;
+ }
+
ret = processor_thermal_send_mbox_read_cmd(to_pci_dev(dev), id, &resp);
if (ret)
return ret;
+ret_resp:
return sysfs_emit(buf, "%llu\n", resp);
}
@@ -461,6 +476,7 @@ int proc_thermal_rfim_add(struct pci_dev *pdev, struct proc_thermal_device *proc
case PCI_DEVICE_ID_INTEL_NVL_H_THERMAL:
case PCI_DEVICE_ID_INTEL_NVL_S_THERMAL:
dlvr_mmio_regs_table = nvl_dlvr_mmio_regs;
+ ddr_data_rate_reg = &nvl_ddr_data_rate_reg;
break;
default:
dlvr_mmio_regs_table = dlvr_mmio_regs;
--
2.52.0
next reply other threads:[~2026-02-23 19:04 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-23 19:04 Srinivas Pandruvada [this message]
2026-03-05 14:42 ` Rafael J. Wysocki
2026-03-09 15:48 ` srinivas pandruvada
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