On Tue, Feb 24, 2026 at 04:27:11PM +0100, Andy Shevchenko wrote:
> As stated in [1] the Baikal platforms are not supported and
> the respective driver code is going to be removed. Remove
> soon be unused bindings.
> 
> Link: https://lore.kernel.org/r/20260224150616.3585591-1-andriy.shevchenko@linux.intel.com [1]
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

This feels like it should have been in a series with the driver removal.
If Krzysztof wants to take it with the driver to avoid warnings in his
tree:
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Otherwise I'll revisit this in a day or two and grab it.

Cheers,
Conor.

> ---
>  .../bindings/cache/baikal,bt1-l2-ctl.yaml     | 63 -------------------
>  1 file changed, 63 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml b/Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml
> deleted file mode 100644
> index ec4f367bc0b4..000000000000
> --- a/Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml
> +++ /dev/null
> @@ -1,63 +0,0 @@
> -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> -# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
> -%YAML 1.2
> ----
> -$id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
> -$schema: http://devicetree.org/meta-schemas/core.yaml#
> -
> -title: Baikal-T1 L2-cache Control Block
> -
> -maintainers:
> -  - Serge Semin <fancer.lancer@gmail.com>
> -
> -description: |
> -  By means of the System Controller Baikal-T1 SoC exposes a few settings to
> -  tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
> -  to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
> -  L2-cache controller block is responsible for the tuning. Its DT node is
> -  supposed to be a child of the system controller.
> -
> -properties:
> -  compatible:
> -    const: baikal,bt1-l2-ctl
> -
> -  reg:
> -    maxItems: 1
> -
> -  baikal,l2-ws-latency:
> -    $ref: /schemas/types.yaml#/definitions/uint32
> -    description: Cycles of latency for Way-select RAM accesses
> -    default: 0
> -    minimum: 0
> -    maximum: 3
> -
> -  baikal,l2-tag-latency:
> -    $ref: /schemas/types.yaml#/definitions/uint32
> -    description: Cycles of latency for Tag RAM accesses
> -    default: 0
> -    minimum: 0
> -    maximum: 3
> -
> -  baikal,l2-data-latency:
> -    $ref: /schemas/types.yaml#/definitions/uint32
> -    description: Cycles of latency for Data RAM accesses
> -    default: 1
> -    minimum: 0
> -    maximum: 3
> -
> -additionalProperties: false
> -
> -required:
> -  - compatible
> -
> -examples:
> -  - |
> -    l2@1f04d028 {
> -      compatible = "baikal,bt1-l2-ctl";
> -      reg = <0x1f04d028 0x004>;
> -
> -      baikal,l2-ws-latency = <1>;
> -      baikal,l2-tag-latency = <1>;
> -      baikal,l2-data-latency = <2>;
> -    };
> -...
> -- 
> 2.50.1
>