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Mon, 23 Feb 2026 22:25:44 -0800 From: Akhil R To: CC: , , , , , , , , , , , , Subject: Re: [PATCH 6/8] dmaengine: tegra: Use iommu-map for stream ID Date: Tue, 24 Feb 2026 11:55:43 +0530 Message-ID: <20260224062543.47660-1-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C3:EE_|BL4PR12MB9536:EE_ X-MS-Office365-Filtering-Correlation-Id: f27304d6-5271-4a53-f276-08de736d9670 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?dnq03Lem+DYPAiUJnT1dVxAlZn/4gtIgR9efRxgdbpwTDGxRLHlbze5iVpGK?= =?us-ascii?Q?oVqzjbgfcKaJRTBET71bH345tXAML/5OZp4jmqYR6/0Un2uahtllGzXVWVWL?= =?us-ascii?Q?AmazUT2m5B97iQ7o6Zd/fPUKUtfbNmX9H9+BYdWCqk/EmIKWXoGwLpbYaPP/?= =?us-ascii?Q?FJEo+VLLsN1nlN53w4hask+WDN2o8dI9Hq3RpeCD56QBc5cRJIawqPZznCLZ?= =?us-ascii?Q?b0l1Jturrn6rr95ufSpVHkWrt+/Btij2hnmvxDfS95Zww6ncKhZlxyV20ScQ?= =?us-ascii?Q?5SQw1yO5LQl1b9HTwL6oD7qgJCPcukYsE9c1KzaphnLF9x+BKF6z3BHzjXoU?= =?us-ascii?Q?2auhlXuL5UQfSxKTXHQpI00mFKI6X3GyN7UT59dISy1m462k/d1btyePErv0?= =?us-ascii?Q?0Ykxc75nWBg1ShxWNNMZabYwzgRwElLUG1d9oDWt7EeYuv3VPrJ1CLieaTRY?= =?us-ascii?Q?qrGATGUi3CzD4+xM1z2IcR1231aBmcw7quVQpbdUF4JUAPMe1RhVwg/yoTmT?= =?us-ascii?Q?2dyvMS7/gvxWozAk4ow1AnvProOaQNLwgowbMp513auVpkZ7Sp3tRMP/zLpI?= =?us-ascii?Q?tq261dKh7hi50Oz5JnSOSSxwM6h9jP7sKz6IEOgGIE33bIlHoD/GOxAEs5U2?= =?us-ascii?Q?SHrm0Zx76KNNiNKgwTgq9ifIjF4uOjTxMIZBf2+pjCa2fdu5DX0YeioOvhcy?= =?us-ascii?Q?e4nm/04g4pdnJBKTLqWPZBrJLngwYPz/RN7QUWrp5DxRGBRBmmXktvkc8qSE?= =?us-ascii?Q?0tAYJAPXLC+DAFrde74KHPGJwN1TJZfWU9dt5U0F7BSmfB6o3+HoyUDBL1Bj?= =?us-ascii?Q?G9MYyuxI0i92+8Qh3dKgIDlAIxeipEqN2KvUz9YMI/TZiKdwXFhhNabdsgSN?= =?us-ascii?Q?msN7tceAHEVEoWLaTKcU9sW0BFx6k2FplXLanXkq+FtPbCyuRQxNu77Gc0Dz?= =?us-ascii?Q?H5Xg9Cn9PdFtr6D880qif482IN+1i0wfgDUMfTpztlDTWR7UC1tn1+tHDznc?= =?us-ascii?Q?jDM5RTQYRvW/bWSOdwtXgA2VrJ4ZiaoSxDgPgq1dp3bs7xEdHwFoBgSKJklm?= =?us-ascii?Q?ycaVjzGrwTpLdAyiju7p74JS72mtxaHP/UeVyokjHNJsroXlPY0I2Kqkw0km?= =?us-ascii?Q?7DUkssmWWKKqzdWQjpOYmAu2YtWW8OZd6KYGaRo9PrKL2RFkVptgikexF7vw?= =?us-ascii?Q?JEaFJYp01CKKftNoehykUMQqJV3uXCWkRZjjTbiUzc6spcqo8jJCiQVjNMTc?= =?us-ascii?Q?cBKUbSpO9cXAC2czvtW69jM+wiYC4ZX8a1KPog+ssn77lkGkZ9wNPt4tZ6FO?= =?us-ascii?Q?tJQYkWTBEL1XEXjUyFgXwa0RKHC07Wd6Lbw99q6rhnQIiNYN5BS15bJKrB+V?= =?us-ascii?Q?kk8ANdqvV1lhtHH3avGvwBLgvTAFkgtBfSEZJ9IHR2R6kychR63A9vFrcrgv?= =?us-ascii?Q?PiVKFYq/8OTYplBal3v+kYYom5YTaN9p0czXqwxi3hk8vcJmd0PW7oirW379?= =?us-ascii?Q?FIwTLAV/ofnM8JagZd5PuSbKq+tazqF0eJjhEAnGsyyhjhRH1O5ysO1n5Ryt?= =?us-ascii?Q?kMbfdxIihumWke9UKl8fPO0cSvIinrXJaAFKp0Hm3dJ42QBPSHqTOgPy57YH?= =?us-ascii?Q?UTK3O/xMUsETnjQPybd+VpLCMGDw3+qZzpaefYsYabq4LiwEtf1rjrOlKakk?= =?us-ascii?Q?0XmltQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: SiCOb/onR1OcX0nj+OBP9iZbtjVaSwBuEMe/FsGbAJgNVIM+FYrEzvaHA7+wEY4MF8yBshBk49Qmi8vQMZSMj30nzioeDg9z2WEkWJmSi2Q25vk6JeC5S5Umc6ZCM/QSGXbq1APHa6KLL01dx6WS7dTauL6O8QjtLT4njm4zxav7JafN0YV18qjtE1Nbfet5WF2StHB0NsbEKTQZ9ObrYul87eV9neFwSQX5hPVuDgac6OW9SyBwT/wrJhcpFracoY86LLY3o+viZ0OA2rDtXM89IPmIE6xY0GiAxeQF3ZtR7/0beNiuBNzg6e+yk2YWHBTN1IURUOX5BPgZYuJIWZMvTfRhXb03/gZZVJI+RoRi30pvOwx4gVpUaKclAFCvtop6ZoWmBKCETHLyISB42Q/5Pdgen8vZfjlor5QDrHvc8kFlhiPzLJx3qlTSeNAN X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2026 06:26:04.5401 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f27304d6-5271-4a53-f276-08de736d9670 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9536 On Tue, 17 Feb 2026 14:52:17 -0500, Frank Li wrote: > On Tue, Feb 17, 2026 at 11:04:55PM +0530, Akhil R wrote: >> Use iommu-map, when provided, to get the stream ID to be programmed >> for each channel. Register each channel separately for allowing it >> to use a separate IOMMU domain for the transfer. >> >> Channels will continue to use the same global stream ID if iommu-map >> property is not present in the device tree. >> >> Signed-off-by: Akhil R >> --- >> drivers/dma/tegra186-gpc-dma.c | 62 +++++++++++++++++++++++++++------- >> 1 file changed, 49 insertions(+), 13 deletions(-) >> >> diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c >> index ce3b1dd52bb3..b8ca269fa3ba 100644 >> --- a/drivers/dma/tegra186-gpc-dma.c >> +++ b/drivers/dma/tegra186-gpc-dma.c >> @@ -15,6 +15,7 @@ >> #include >> #include >> #include >> +#include >> #include >> #include >> #include >> @@ -1403,9 +1404,12 @@ static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id) >> static int tegra_dma_probe(struct platform_device *pdev) >> { >> const struct tegra_dma_chip_data *cdata = NULL; >> + struct tegra_dma_channel *tdc; >> + struct tegra_dma *tdma; >> + struct dma_chan *chan; >> + bool use_iommu_map = false; >> unsigned int i; >> u32 stream_id; >> - struct tegra_dma *tdma; >> int ret; >> >> cdata = of_device_get_match_data(&pdev->dev); >> @@ -1433,9 +1437,12 @@ static int tegra_dma_probe(struct platform_device *pdev) >> >> tdma->dma_dev.dev = &pdev->dev; >> >> - if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { >> - dev_err(&pdev->dev, "Missing iommu stream-id\n"); >> - return -EINVAL; >> + use_iommu_map = of_property_present(pdev->dev.of_node, "iommu-map"); >> + if (!use_iommu_map) { >> + if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { >> + dev_err(&pdev->dev, "Missing iommu stream-id\n"); >> + return -EINVAL; >> + } >> } >> >> ret = device_property_read_u32(&pdev->dev, "dma-channel-mask", >> @@ -1449,7 +1456,7 @@ static int tegra_dma_probe(struct platform_device *pdev) >> >> INIT_LIST_HEAD(&tdma->dma_dev.channels); >> for (i = 0; i < cdata->nr_channels; i++) { >> - struct tegra_dma_channel *tdc = &tdma->channels[i]; >> + tdc = &tdma->channels[i]; >> >> /* Check for channel mask */ >> if (!(tdma->chan_mask & BIT(i))) >> @@ -1469,10 +1476,6 @@ static int tegra_dma_probe(struct platform_device *pdev) >> >> vchan_init(&tdc->vc, &tdma->dma_dev); >> tdc->vc.desc_free = tegra_dma_desc_free; >> - >> - /* program stream-id for this channel */ >> - tegra_dma_program_sid(tdc, stream_id); >> - tdc->stream_id = stream_id; >> } >> >> ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(cdata->addr_bits)); >> @@ -1517,20 +1520,53 @@ static int tegra_dma_probe(struct platform_device *pdev) >> return ret; >> } >> >> + list_for_each_entry(chan, &tdma->dma_dev.channels, device_node) { >> + struct device *chdev = &chan->dev->device; >> > why no use > for (i = 0; i < cdata->nr_channels; i++) { > struct tegra_dma_channel *tdc = &tdma->channels[i]; I thought this would ensure that we try to configure only the channels where the chan_dev and vchan are initialized. I understand that it is not probable in the current implementation that we will have channels which are uninitialized, but I felt this a better approach. Do you see any disadvantage in using the channels list? >> + >> + tdc = to_tegra_dma_chan(chan); >> + if (use_iommu_map) { >> + chdev->coherent_dma_mask = pdev->dev.coherent_dma_mask; >> + chdev->dma_mask = &chdev->coherent_dma_mask; >> + chdev->bus = pdev->dev.bus; >> + >> + ret = of_dma_configure_id(chdev, pdev->dev.of_node, >> + true, &tdc->id); >> + if (ret) { >> + dev_err(chdev, "Failed to configure IOMMU for channel %d: %d\n", >> + tdc->id, ret); >> + goto err_unregister; >> + } >> + >> + if (!tegra_dev_iommu_get_stream_id(chdev, &stream_id)) { >> + dev_err(chdev, "Failed to get stream ID for channel %d\n", >> + tdc->id); >> + goto err_unregister; >> + } >> + >> + chan->dev->chan_dma_dev = true; >> + } >> + >> + /* program stream-id for this channel */ >> + tegra_dma_program_sid(tdc, stream_id); >> + tdc->stream_id = stream_id; >> + } >> + >> ret = of_dma_controller_register(pdev->dev.of_node, >> tegra_dma_of_xlate, tdma); >> if (ret < 0) { >> dev_err_probe(&pdev->dev, ret, >> "GPC DMA OF registration failed\n"); >> - >> - dma_async_device_unregister(&tdma->dma_dev); >> - return ret; >> + goto err_unregister; >> } >> >> - dev_info(&pdev->dev, "GPC DMA driver register %lu channels\n", >> + dev_info(&pdev->dev, "GPC DMA driver registered %lu channels\n", >> hweight_long(tdma->chan_mask)); >> >> return 0; >> + >> +err_unregister: >> + dma_async_device_unregister(&tdma->dma_dev); > > Can you use dmaenginem_async_device_register() to simple error path? > > Frank Agree. I will update it to use this function instead. >> + return ret; >> } >> >> static void tegra_dma_remove(struct platform_device *pdev) >> -- Regards, Akhil