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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4160cf239e0sm978431fac.1.2026.02.25.20.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Feb 2026 20:52:22 -0800 (PST) From: Deepti Jaggi Subject: [PATCH v4 0/2] arm64: dts: qcom: Introduce sa8255p platform device tree Date: Wed, 25 Feb 2026 20:51:05 -0800 Message-Id: <20260225-b4-scmi-upstream-v4-0-50cfba9e6a0f@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIADnRn2kC/x3MQQ5AMBBA0avIrE1CU5W6ilhoDWbRkg4iEXfXW L7F/w8IJSaBrngg0cXCW8zQZQF+HeNCyFM2qEqZSimNTqP4wHjuciQaA3rbWt/UxmpXQ872RDP f/7If3vcDHItZaGIAAAA= X-Change-ID: 20260224-b4-scmi-upstream-c979c51694b1 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Deepti Jaggi , Nikunj Kela , Shazad Hussain , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772081541; l=7383; i=deepti.jaggi@oss.qualcomm.com; s=20250501; h=from:subject:message-id; bh=tFhfD1nC84Tm9n1pRJ1GG8pmTOb+/85gGuxTTClLnxY=; b=VIcIE1ljQoet1C5k9FDCTFwoR6R54zwZXQq0pqZaPykHue4EDBBcDk1eAyD9mRO796PgcZLyv t45a1O2aE0MBnNVV9MRdqYQUV0rKQE+29kvitYqpuD6a5MaDVTWsrrc X-Developer-Key: i=deepti.jaggi@oss.qualcomm.com; a=ed25519; pk=+b3H5UC/u0pUK5+btJ+35nW+6vKwJV1CfjJ1CJWuOZw= X-Authority-Analysis: v=2.4 cv=XI49iAhE c=1 sm=1 tr=0 ts=699fd188 cx=c_pps a=wURt19dY5n+H4uQbQt9s7g==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=OqDjb2b6Uua3qTf0ZKoA:9 a=QEXdDO2ut3YA:10 a=-UhsvdU3ccFDOXFxFb4l:22 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjI2MDA0MCBTYWx0ZWRfX+4JUYDzUwGMx HYC93d2s7yHS/+dIsfvA5zx3ifKE8fRo2oqnVg20AVNugGVw271rnZ/QNDitUEb8LnWtzqGr29a RQO8Nx96fVblqN1erlZbDZNwKn2GvQDGokKNtelEFaLIMdRYl9wgqJo/Aaqj70wGUYK54ajG996 ZFF7NyiAcaz68fJOwzy2G9wj1lVAf11sASsv8cmo8A8uiPjsn54+7iH2eU2HTWW3tf3NID3mK3l NAqtLZjAUVsxL8JFIALIJyWfUS/v/0+PlunpP5+9pRSiVvM7l9gkqz3O2+zWPv2n/TPeAwVjUY8 H1nzCh9foNK6OpGXsBqW843e6q4z3Fv3Ukazx//Mn9KBvh/Xfodc2TFvdBGg2KZ6DsJsoqCpO6K Fb2DSmml95dS48KJkwoJM4YxA8+9YKqiYeQmzLM6PZFb+j3C7FWJ6PHAfx4qDFDJskM3XlYKcWM 4XODayJvZQwkoAWYbCA== X-Proofpoint-ORIG-GUID: h6MxlTvddSZjaLWgJ5kksreKC6_olA8Q X-Proofpoint-GUID: h6MxlTvddSZjaLWgJ5kksreKC6_olA8Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-25_04,2026-02-25_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1011 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602260040 Introduce initial device tree support for sa8255p Qualcomm's automotive infotainment SoC and its reference board: sa8255p-ride. Use SCMI power, reset, performance, and sensor protocols to manage resources such as clocks, regulators, interconnects, and PHYs. Operate the SCMI server stack in an SMP-enabled VM, using the Qualcomm SMC/HVC transport driver for communication. Instantiate multiple SCMI instances to support parallelism and assign each device a dedicated SCMI channel and Tx/Rx doorbells. Group resource operations to improve abstraction and minimize SCMI server requests. Apply the design as presented at LinaroConnect 2024 conference[1]. Features added and enabled: - CPUs with cpufreq - Interrupt-controller with PDC wakeup support - Timers, TCSR - Reserved memory regions - TLMM - QuP with uart - SMMU - Watchdog - TSENS (Thermal Sensors) - PMIC support - IPCC - Random number generator (RNG) - UFS - PCIE Architecture: +--------------------+ | Shared Memory | | | | +----------------+ | +-------------------+ +--------------------------------+ +-+-> | uart-shmem | <-+-+ | Linux | | SCMI Platform | | | +----------------+ | | | +----------+ | | | | | | | | | | UART | | | +------------+ f +----------+ | | | | | | | Driver | | | | Drivers <---+ SCMI | | e | | | | | | +--+----^--+ | | | (clks, | g | Server +-+-------------------+ | | | | | | | | | icc paths, +---> | | h | | | b|k | a| l| | | | tlmm, | +--^-----+-+ | | | | | | | | | | etc.) | | | | | | | | | +---v----+----+ | | | | | | | | | +------------+--+ UART SCMI | | | +------------+ | | | | | | | | INSTANCE | | | | | | | | | +-^-----+-----+ | | | | | | | | | | | | +----------------------+-----+---+ | | +----+-----+--------+ | | | | | | | | | +--------------------+ | | d|IRQ i|HVC j|IRQ c|HVC | | | | | | | | +-----------------------+-----v----------------------------------------------------------------------+-----v--------+ | | | | | | | HYPERVISOR | | | | | +-------------------------------------------------------------------------------------------------------------------+ +--------+ +--------+ +-----------+ | CLOCK | | TLMM | | UART | +--------+ +--------+ +-----------+ --- Patch 1: Changes in v4: Added the patch in this series. Rebased on linux-next Link to v3 https://lore.kernel.org/all/20250423003845.3980330-1-quic_djaggi@quicinc.com/ Changes in v3: Removed the patches from original series[2] Changes in v2: Added Reviewed-by tag Patch 2: Changes in v4: Added the patch in this series Updates to commit text Sorted clocks in alphabetical order Added dcvsh interrupts Hystersis value changed to 10000 for soc thermal zones Deleted sa8255p-scmi.dtsi and scmi nodes moved under firmware node to sa8255p.dtsi Changes to scmi shmem nodes - removed from sram and added to reserved region Changes to copyright Added address cells and size cells to interrupt controller/intc Added dma-coherent property to smmu Added pcie and ufs support Link to v3 https://lore.kernel.org/all/20250422231249.871995-1-quic_djaggi@quicinc.com/ Changes in v3: Removed the patches from original series [2]. Added arm,max-msg and arm,max-msg-size DT property in scmi nodes. Changed max-rx-timeout-ms to arm,max-rx-timeout-ms in scmi nodes. Updated commit text. Reordered range property for qupv3_id_0, qupv3_id_1 and qupv3_id_3 nodes. Reordered vendor property(#qcom,sensors) for tsens* nodes. Changed cache labels to lower case. Removed unused i2c,spi and tlmm nodes. Updated reserved memory nodes. Changes in v2: Removed scmichannels label and alias Modified scmi node name to conform to schema Moved status property to be the last one in scmi instances Changed to lower case for cpu labels Added fallback compatible for tlmm node [1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte [2]: https://lore.kernel.org/all/20240903220240.2594102-1-quic_nkela@quicinc.com/ Signed-off-by: Deepti Jaggi --- Nikunj Kela (2): dt-bindings: arm: qcom: add SA8255p Ride board arm64: dts: qcom: add initial support for qcom sa8255p-ride Documentation/devicetree/bindings/arm/qcom.yaml | 5 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi | 80 + arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 161 + arch/arm64/boot/dts/qcom/sa8255p.dtsi | 4861 +++++++++++++++++++++++ 5 files changed, 5108 insertions(+) --- base-commit: af98e93c5c39e6d0b87b42f0a32dd3066f795718 change-id: 20260224-b4-scmi-upstream-c979c51694b1 Best regards, -- Deepti Jaggi