From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9495238E5C4; Wed, 25 Feb 2026 09:20:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772011256; cv=none; b=l8ZhetL8/iLgsuDfIMwRP9Nrh3rSpMwVDL5fzl6+Ot/x/kgVI3Tfv57BrP7xdwVzHEbP+LSsPltIgoBorZj7PIletM6xSZDXTwt3bFyufEs0TEsBuuif/eoT/Oe2Pxu5me8JH2HU+o7rcXBrI/jX9Wp67YFiNVLE7dhFzWmPvB8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772011256; c=relaxed/simple; bh=1wg2w5Y5/YzQPQzVr+3ynFChKDaTwYad7mRHpb7T0TQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o5srob9RWWMLX+9HM6ApifgYG4C57hdtRR7pzmoywt2wWzbcsdMSygpW8L3FCo9V9xp+onpnh+NuIUpzS7JMMSHwSiDj22RXiHwcqSQC8M5ch0cUlnC7TOHYhZ4HrUFHY6fxTFtxn5nXqKGa9Fk/xETqpNO2jWB5lpSkb3q1lA0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ucyZelTL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ucyZelTL" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5FA47C2BCB7; Wed, 25 Feb 2026 09:20:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772011256; bh=1wg2w5Y5/YzQPQzVr+3ynFChKDaTwYad7mRHpb7T0TQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ucyZelTLPocdMfhxnHrWFYcQU4O36uEVnHyFGCcZxHZ23XZ1Fs01rN/xqkDTh3n/7 qOb4LdDj9NauLxFtGzcM58uVv9dQ611qBAlY/x21Lk+ePHJxJgZcEizn6hx1YT7eAL VnTdJLt9UVlTqt32aK+VZfI2nDVGxXb0JU9mLKEtZNOY2xJxVJn7QKu+GYwhjdPUH5 yd1iCXByxKS6DqlP9sgcrpgVWA9yhfjkPy0DDV0Kyv9rKz8HIPblrTl+3Q6FjXRYcU UTa1KP5lMKpEHXyzt2BkrkT/FBLW2GbU7ay/n12PCk7kV2fqbloy2ksKaHSEHb1r8b yL83I59QLbEZg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 543C3EFD216; Wed, 25 Feb 2026 09:20:56 +0000 (UTC) From: Jan Petrous via B4 Relay Date: Wed, 25 Feb 2026 10:20:37 +0100 Subject: [PATCH v6 5/5] stmmac: s32: enable support for Multi-IRQ mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260225-dwmac_multi_irq-v6-5-245bf1d7110c@oss.nxp.com> References: <20260225-dwmac_multi_irq-v6-0-245bf1d7110c@oss.nxp.com> In-Reply-To: <20260225-dwmac_multi_irq-v6-0-245bf1d7110c@oss.nxp.com> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, devicetree@vger.kernel.org, rmk+kernel@armlinux.org.uk, "Jan Petrous (OSS)" X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772011254; l=4698; i=jan.petrous@oss.nxp.com; s=20240922; h=from:subject:message-id; bh=VhNXhFN3LNj9piUSrvcU0j8rDNgFhxjzRPwBQhKPqME=; b=tG4OPocKqVIacnzg6C8UUg/DR2vaS/X/hta0AyweSYYSjJMzjIGZkxO8P5gK8neG2nzpjZwAT N6pBZ5ltd6hDKEerKCfVeJH9gdRvqiShQiZCBgp+lwc+r83oWkdK9Lj X-Developer-Key: i=jan.petrous@oss.nxp.com; a=ed25519; pk=Ke3wwK7rb2Me9UQRf6vR8AsfJZfhTyoDaxkUCqmSWYY= X-Endpoint-Received: by B4 Relay for jan.petrous@oss.nxp.com/20240922 with auth_id=217 X-Original-From: "Jan Petrous (OSS)" Reply-To: jan.petrous@oss.nxp.com From: "Jan Petrous (OSS)" Based on previous changes in platform driver, the vendor glue driver can enable Multi-IRQ mode, if needed. To get enabled Multi-IRQ mode for dwmac-s32, the driver checks: 1) property of 'snps,mtl-xx-config' subnode defines 'snps,xx-queues-to-use' bigger then one, ie: ethernet@4033c000 { compatible = "nxp,s32g2-dwmac"; ... snps,mtl-rx-config = <&mtl_rx_setup>; ... mtl_rx_setup: rx-queues-config { snps,rx-queues-to-use = <2>; }; 2) queue based IRQs are set, ie: ethernet@4033c000 { compatible = "nxp,s32g2-dwmac"; ... interrupts = , /* CHN 0: tx, rx */ , , /* CHN 1: tx, rx */ , ; interrupt-names = "macirq", "tx-queue-0", "rx-queue-0", "tx-queue-1", "rx-queue-1"; If those prerequisites are met, the driver switch to Multi-IRQ mode, using per-queue IRQs for rx/tx data pathr: [ 1.387045] s32-dwmac 4033c000.ethernet: Multi-IRQ mode (per queue IRQs) selected Now the driver owns all queues IRQs: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac 30: 0 0 0 0 0 0 0 0 GICv3 91 Level eth0:rx-0 31: 0 0 0 0 0 0 0 0 GICv3 93 Level eth0:rx-1 32: 0 0 0 0 0 0 0 0 GICv3 95 Level eth0:rx-2 33: 0 0 0 0 0 0 0 0 GICv3 97 Level eth0:rx-3 34: 0 0 0 0 0 0 0 0 GICv3 99 Level eth0:rx-4 35: 0 0 0 0 0 0 0 0 GICv3 90 Level eth0:tx-0 36: 0 0 0 0 0 0 0 0 GICv3 92 Level eth0:tx-1 37: 0 0 0 0 0 0 0 0 GICv3 94 Level eth0:tx-2 38: 0 0 0 0 0 0 0 0 GICv3 96 Level eth0:tx-3 39: 0 0 0 0 0 0 0 0 GICv3 98 Level eth0:tx-4 Otherwise, if one of the prerequisite don't met, the driver continue with MAC IRQ mode: [ 1.387045] s32-dwmac 4033c000.ethernet: MAC IRQ mode selected And only MAC IRQ will be attached: root@s32g399aevb3:~# grep eth /proc/interrupts 29: 0 0 0 0 0 0 0 0 GICv3 89 Level eth0:mac What represents the original MAC IRQ mode and is fully backward compatible. Reviewed-by: Matthias Brugger Signed-off-by: Jan Petrous (OSS) --- drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c | 36 ++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c index af594a096676..03e014c10d3f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c @@ -2,7 +2,7 @@ /* * NXP S32G/R GMAC glue layer * - * Copyright 2019-2024 NXP + * Copyright 2019-2026 NXP * */ @@ -110,6 +110,37 @@ static void s32_gmac_exit(struct device *dev, void *priv) clk_disable_unprepare(gmac->rx_clk); } +static void s32_gmac_validate_multi_irq(struct device *dev, + struct plat_stmmacenet_data *plat, + struct stmmac_resources *res) +{ + int i; + + /* RX IRQs */ + STMMAC_FOREACH_MTL_QUEUE(i, plat->rx_queues_to_use) { + if (res->rx_irq[i] <= 0) { + dev_dbg(dev, "Missing RX queue %d interrupt\n", i); + goto no_multi_irq; + } + } + + /* TX IRQs */ + STMMAC_FOREACH_MTL_QUEUE(i, plat->tx_queues_to_use) { + if (res->tx_irq[i] <= 0) { + dev_dbg(dev, "Missing TX queue %d interrupt\n", i); + goto no_multi_irq; + } + } + + plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; + dev_info(dev, "Multi-IRQ mode (per queue IRQs) selected\n"); + return; + +no_multi_irq: + plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN; + dev_info(dev, "MAC IRQ mode selected\n"); +} + static int s32_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat; @@ -165,6 +196,9 @@ static int s32_dwmac_probe(struct platform_device *pdev) plat->core_type = DWMAC_CORE_GMAC4; plat->pmt = 1; plat->flags |= STMMAC_FLAG_SPH_DISABLE; + + s32_gmac_validate_multi_irq(dev, plat, &res); + plat->rx_fifo_size = 20480; plat->tx_fifo_size = 20480; -- 2.47.0