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X-CSE-ConnectionGUID: CuTHRctdSuOo+CeX/pVyrg== X-CSE-MsgGUID: l01JtG8PRkGjfh2LIX/aCQ== X-IronPort-AV: E=Sophos;i="6.21,310,1763449200"; d="scan'208";a="61258794" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Feb 2026 01:56:20 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.87.152) by chn-vm-ex1.mchp-main.com (10.10.87.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.35; Wed, 25 Feb 2026 01:55:50 -0700 Received: from che-lt-i67131.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 25 Feb 2026 01:55:40 -0700 From: Manikandan Muralidharan To: , , , , , , , , , , , , , , , , , , , , , , , , , CC: Ryan Wanner , Manikandan Muralidharan Subject: [PATCH 1/6] ARM: dts: microchip: sama7d65: add LCD controller Date: Wed, 25 Feb 2026 14:24:25 +0530 Message-ID: <20260225085430.480052-2-manikandan.m@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260225085430.480052-1-manikandan.m@microchip.com> References: <20260225085430.480052-1-manikandan.m@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Ryan Wanner Add support for LCD controller node Signed-off-by: Ryan Wanner Signed-off-by: Manikandan Muralidharan --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 26 +++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi index e21556f46384..b2fe76115aec 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -278,6 +278,32 @@ sdmmc1: mmc@e1208000 { status = "disabled"; }; + xlcdc: lcd-controller@e1400000{ + compatible = "microchip,sama7d65-xlcdc"; + reg = <0xe1400000 0x2000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>, <&clk32k 1>; + clock-names = "periph_clk", "sys_clk", "slow_clk"; + status = "disabled"; + + display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pwm { + compatible = "atmel,hlcdc-pwm"; + #pwm-cells = <3>; + }; + }; + aes: crypto@e1600000 { compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes"; reg = <0xe1600000 0x100>; -- 2.25.1