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[142.162.112.119]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8cbbf72d3casm601180485a.42.2026.02.27.16.06.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 16:06:30 -0800 (PST) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1vw7qo-00000001WqD-1LkU; Fri, 27 Feb 2026 20:06:30 -0400 Date: Fri, 27 Feb 2026 20:06:30 -0400 From: Jason Gunthorpe To: Robin Murphy Cc: Alexey Kardashevskiy , x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-pci@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Sean Christopherson , Paolo Bonzini , Andy Lutomirski , Peter Zijlstra , Bjorn Helgaas , Dan Williams , Marek Szyprowski , Andrew Morton , Catalin Marinas , Michael Ellerman , Mike Rapoport , Tom Lendacky , Ard Biesheuvel , Neeraj Upadhyay , Ashish Kalra , Stefano Garzarella , Melody Wang , Seongman Lee , Joerg Roedel , Nikunj A Dadhania , Michael Roth , Suravee Suthikulpanit , Andi Kleen , Kuppuswamy Sathyanarayanan , Tony Luck , David Woodhouse , Greg Kroah-Hartman , Denis Efremov , Geliang Tang , Piotr Gregor , "Michael S. Tsirkin" , Alex Williamson , Arnd Bergmann , Jesse Barnes , Jacob Pan , Yinghai Lu , Kevin Brodsky , Jonathan Cameron , "Aneesh Kumar K.V (Arm)" , Xu Yilun , Herbert Xu , Kim Phillips , Konrad Rzeszutek Wilk , Stefano Stabellini , Claire Chang , linux-coco@lists.linux.dev, iommu@lists.linux.dev, Jiri Pirko Subject: Re: [PATCH kernel 6/9] x86/dma-direct: Stop changing encrypted page state for TDISP devices Message-ID: <20260228000630.GN44359@ziepe.ca> References: <20260225053806.3311234-1-aik@amd.com> <20260225053806.3311234-7-aik@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Feb 25, 2026 at 05:08:37PM +0000, Robin Murphy wrote: > I guess this comes back to the point I just raised on the previous patch - > the current assumption is that devices cannot access private memory at all, > and thus phys_to_dma() is implicitly only dealing with the mechanics of how > the given device accesses shared memory. Once that no longer holds, I don't > see how we can find the right answer without also consulting the relevant > state of paddr itself, and that really *should* be able to be commonly > abstracted across CoCo environments. Definately, I think building on this is a good place to start https://lore.kernel.org/all/20260223095136.225277-2-jiri@resnulli.us/ Probably this series needs to take DMA_ATTR_CC_DECRYPTED and push it down into the phys_to_dma() and make the swiotlb shared allocation code force set it. But what value is stored in the phys_addr_t for shared pages on the three arches? Does ARM and Intel set the high GPA/IPA bit in the phys_addr or do they set it through the pgprot? What does AMD do? ie can we test a bit in the phys_addr_t to reliably determine if it is shared or private? > > pci_device_add() enforces the FFFF_FFFF coherent DMA mask so > > dma_alloc_coherent() fails when SME=on, this is how I ended up fixing > > phys_to_dma() and not quite sure it is the right fix. Does AMD have the shared/private GPA split like ARM and Intel do? Ie shared is always at a high GPA? What is the SME mask? Jason