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Sat, 28 Feb 2026 15:04:47 +0000 (UTC) Date: Sat, 28 Feb 2026 16:04:47 +0100 From: Borislav Petkov To: Yazen Ghannam Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, tony.luck@intel.com, x86@kernel.org Subject: Re: [PATCH] x86/mce/amd, EDAC/mce_amd: Add new SMCA bank types Message-ID: <20260228150447.GCaaMED_7sbC3OvDsL@fat_crate.local> References: <20260202172158.2455749-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260202172158.2455749-1-yazen.ghannam@amd.com> On Mon, Feb 02, 2026 at 05:21:58PM +0000, Yazen Ghannam wrote: > Recognize new SMCA bank types and include their short names for sysfs > and long names for decoding. > > Signed-off-by: Yazen Ghannam > --- > arch/x86/include/asm/mce.h | 11 +++++++++++ > arch/x86/kernel/cpu/mce/amd.c | 21 +++++++++++++++++++++ > drivers/edac/mce_amd.c | 10 ++++++++++ > 3 files changed, 42 insertions(+) > > diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h > index 2d98886de09a..6e1f10ca053f 100644 > --- a/arch/x86/include/asm/mce.h > +++ b/arch/x86/include/asm/mce.h > @@ -370,13 +370,24 @@ enum smca_bank_types { > SMCA_NBIO, /* Northbridge IO Unit */ > SMCA_PCIE, /* PCI Express Unit */ > SMCA_PCIE_V2, > + SMCA_MPRAS, /* MP for RAS */ > SMCA_XGMI_PCS, /* xGMI PCS Unit */ > + SMCA_SSBDCI, /* Die to Die Interconnect */ > SMCA_NBIF, /* NBIF Unit */ > SMCA_SHUB, /* System HUB Unit */ > SMCA_SATA, /* SATA Unit */ > SMCA_USB, /* USB Unit */ > + SMCA_MPDACC, /* MP for Data Acceleration */ > + SMCA_MPM, /* Microprocessor Manageability Core */ > + SMCA_MPASP, /* AMD Secure Processor */ > + SMCA_MPASP_V2, > + SMCA_MPART, /* AMD Root of Trust Microprocessor */ > + SMCA_DACC_FE, /* Data Acceleration Front-end */ > + SMCA_DACC_BE, /* Data Acceleration Back-end */ > SMCA_USR_DP, /* Ultra Short Reach Data Plane Controller */ > SMCA_USR_CP, /* Ultra Short Reach Control Plane Controller */ > + SMCA_EDDR5CMN, /* eDDR5 CMN */ > + SMCA_PCIE_PL, /* PCIe Link */ > SMCA_GMI_PCS, /* GMI PCS Unit */ > SMCA_XGMI_PHY, /* xGMI PHY Unit */ > SMCA_WAFL_PHY, /* WAFL PHY Unit */ That ordering looks rather random. Does it matter which enum number a bank type is? If not, let's sort them alphabetically for easier reading... In the remaining places too. -- Regards/Gruss, Boris. https://people.kernel.org/tglx/notes-about-netiquette