From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-172.mta0.migadu.com (out-172.mta0.migadu.com [91.218.175.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 413BD239E80 for ; Sat, 28 Feb 2026 20:47:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772311671; cv=none; b=lnL+qJ5E6rzrgrZO8xN1+HqZuR8qrz8vHAQ4cK20L/+c7vGJDVWXzDuK1lZFcvskRqVu961OSDD4TJpITtrBMszCFD/cs4WEQ2r8HdnIbXWHxBqTBeOTEVYVce/cHmjFyRoi/RISn7tIKRv+lsVZJ5ZThoXlM9d66tKRtHTUab0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772311671; c=relaxed/simple; bh=vN79aVq15KJmINuT84+yvI/rNP53bO1GbNxLL6+n1X4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ii3mARjwD0MW2S4YDqS9yHpZKRai8WUOYUbVuS2S8G4F6BrlDmW0/IBSbHGsAcESpgS2JrrS2PUsQO6OJV7KLm9TJgHvAU2YT8fGIhb6YpidDIUxMW4xgQcDYD2M29Ih4+z9pbe7ugKpcRTo7RvHj7ka25lBzOSzJBw926++sQs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool; spf=pass smtp.mailfrom=packett.cool; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b=Icwlohg0; arc=none smtp.client-ip=91.218.175.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=packett.cool Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=packett.cool Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=packett.cool header.i=@packett.cool header.b="Icwlohg0" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=packett.cool; s=key1; t=1772311667; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RG3ZEWSeGQFYP6X+wKEUzoO+lwsoqVPpKdpIj2KNtZg=; b=Icwlohg0Z17tmo7s/HYVjyK+RfW6dGxe5tDSC9i+9ENJBpTt/nPaSjriHhFcf2WQv8pbr9 7OoydCwIcgMRFw9/Ga5h7cIVY+qWLRGjOdWPqghYqEiCGgI52qVdOSA+/jUZ5GQ4VBYT1S o9vdyF2j0NWekwY3A0trkI9+1/rHWdP3nog643kVTRUxp6uP8+hgBEOetsyCeX3V0PpQk4 4Dd0m4KTbdMwAKj6PLYzaYrhCRD9OHH64lWtRbqwBEOJKv0el8T3KpDpdpvptFCsc4FcIZ /cNQpvZ34SvclVDfzUFQFNPSSiOCzoAqEBXOysrXNb2fwbADbLkIuUxIZvs+WQ== From: Val Packett To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adam Skladowski , Dmitry Baryshkov , Marijn Suijten Cc: Val Packett , linux-arm-msm@vger.kernel.org, phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio , Yedaya Katsman Subject: [PATCH v2 6/6] arm64: dts: qcom: sm6125: Add missing MDSS core reset Date: Sat, 28 Feb 2026 17:41:32 -0300 Message-ID: <20260228204638.11705-7-val@packett.cool> In-Reply-To: <20260228204638.11705-1-val@packett.cool> References: <20260228204638.11705-1-val@packett.cool> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Migadu-Flow: FLOW_OUT To make sure the display subsystem starts in a predictable state, we need to reset it. Otherwise, unpredictable issues can happen, e.g. on the xiaomi-laurel-sprout smartphone DSI would not work on boot. Wire up the reset to fix. Fixes: 0865d23a0226 ("arm64: dts: qcom: sm6125: Add display hardware nodes") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Tested-by: Yedaya Katsman Signed-off-by: Val Packett --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 80c42dff5399..a22374e5a17f 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -1238,6 +1238,8 @@ mdss: display-subsystem@5e00000 { "ahb", "core"; + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + power-domains = <&dispcc MDSS_GDSC>; iommus = <&apps_smmu 0x400 0x0>; @@ -1437,6 +1439,7 @@ dispcc: clock-controller@5f00000 { power-domains = <&rpmpd RPMPD_VDDCX>; #clock-cells = <1>; + #reset-cells = <1>; #power-domain-cells = <1>; }; -- 2.52.0