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Sat, 28 Feb 2026 23:09:42 -0800 (PST) From: Xueyuan Chen To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Chen , Fugang Duan Cc: Gary Yang , CIX Linux Kernel Upstream Group , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Xueyuan Chen Subject: [PATCH v4 3/3] arm64: dts: cix: add src syscon nodes for sky1 resets Date: Sun, 1 Mar 2026 15:09:10 +0800 Message-Id: <20260301070910.6169-4-xueyuan.chen21@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260301070910.6169-1-xueyuan.chen21@gmail.com> References: <20260301070910.6169-1-xueyuan.chen21@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the SRC blocks for the CIX Sky1 SoC. These blocks provide reset capabilities to various peripherals across the S0 and S5 domain. Signed-off-by: Gary Yang [Xueyuan Chen: Refactored to pure syscon nodes to fix v3 review issues] Signed-off-by: Xueyuan Chen --- arch/arm64/boot/dts/cix/sky1.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index fb8c826bbc97..6ad5dc368a66 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -348,6 +348,12 @@ i3c1: i3c@4100000 { status = "disabled"; }; + src_fch: reset-controller@4160000 { + compatible = "cix,sky1-src-fch", "syscon"; + reg = <0x0 0x04160000 0x0 0x90>; + #reset-cells = <1>; + }; + iomuxc: pinctrl@4170000 { compatible = "cix,sky1-pinctrl"; reg = <0x0 0x04170000 0x0 0x1000>; @@ -568,6 +574,12 @@ ppi_partition1: interrupt-partition-1 { }; }; + src_s5: reset-controller@16000000 { + compatible = "cix,sky1-src-s5", "syscon"; + reg = <0x0 0x16000000 0x0 0x1000>; + #reset-cells = <1>; + }; + iomuxc_s5: pinctrl@16007000 { compatible = "cix,sky1-pinctrl-s5"; reg = <0x0 0x16007000 0x0 0x1000>; -- 2.43.0