From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E16133E35C for ; Tue, 3 Mar 2026 23:25:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772580357; cv=none; b=gVwV055j7JZnMJoDheqnz/e14kwiLxst9BZlyez3OXcF3sQOOMugF7Uv+QI69lgquE9QEDWRqpU9CKwEforQ069pYpjd6KANV/OBDmlET7JfHINB+zigpHZUPL5qMiVAXqpL5zbyZRf2JwBd0YXOWqalwHYEYZgOIx0m8YkeAnA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772580357; c=relaxed/simple; bh=juTqYkup/by3DgOkN6qLT4McKLHDc5uf8jqpeji0c8k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jQ/msgRzlSTCZbOvcGNp7Cxp2DXTovE1eiDLWxKMJfcX60es0nd4yNgZGotBS6/sDTlzRrjCXbbhAXS6dLDigSBiI7oVw1po5dzfpyGR5Foz+zgGJ7udHEHQfVfOR6ArbQNhgBx0h2VRjAQB9WA69DSOG37kn4NicG+AACG1ayA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DP5gFLiK; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DP5gFLiK" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4806bf39419so52772915e9.1 for ; Tue, 03 Mar 2026 15:25:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772580355; x=1773185155; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f0VDTq5+YnLJ0nZqtFumq/na1fPGtAhpN+2pmOfdQ2I=; b=DP5gFLiK9moR80geGraIO36WmmvxBYZXOem4UsiIVId2aOwNdicYo3zMovY55NTPLn RFrli+0LDMTHSs2AzM49JU6d1Cm6e9oLDek18Q7LO7Gxz0cbAbZct95IyGjUGjBvDFga y5vubYKX1d+AUnhQVX415bl9KVm0gW0I2ZW130U9Hzvbp25kIEidIsKa5sjiI3wmmW6v ck/aulYGDEwOCdk0qAPGBRCZC9opI1gVwH/+My3SslZrKqiWBA2A2PBhz+IgPDnQSaHE iIdCNLIlK1c0i+GHSd5tlKryrUuaoY8qmtCwbvNcyMBoB+Xksuooe1vwUKwkhnOlpszC b0yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772580355; x=1773185155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=f0VDTq5+YnLJ0nZqtFumq/na1fPGtAhpN+2pmOfdQ2I=; b=sAEwGcd92avDzM8cR/nv+d24T4DInFrGfk983gHQ5YyiK355gwfHxmASwOsiGxPE3l unEgccbd0qPQ41+/fk7z/7LAhdDpZVnEw2AsXYVe8TgXvfqTKNPVZf/XLWj6achBqZ8Q SG1J+s8DxcmaZRZ+jD5g6BbUOaOx8Gx+6t+47ah7mkmhzGqO4wRWNUDX/oSRSvOCI98s k1SJA9MGw6FZX/l2bw7JgQjwpYy/aTlRbq3H86bfPJDtivd8oWT7PziH1SnXUS8ovNcQ t88aSKy6ZRMLJMmizxhEC84WIpCJI3h8yRI7vX1SK7PXbz8avgqNWkOqu93z2XQO4Tsn bgow== X-Forwarded-Encrypted: i=1; AJvYcCV8r8NwRY9qIXrBO1Sssxpe+5ljtEWpbZ2uTJPGQy85yXXuukURq/zlLcHywMealxFEcUkvfKie0DFSSys=@vger.kernel.org X-Gm-Message-State: AOJu0YzhlwrDLhX+OiGJDneqoSwuVaG3vImq173dM/xm+abateo2AdQv B9E1QCVy0KazW2uwVlcx/D8joM1i3d6Lze9SNlk8/1DSkwjl/zc4C6d1 X-Gm-Gg: ATEYQzwAuz+u7xWWE29y+3Xt/7n9dAaog5vZLYt/129uaUeQB7y98PvSVkMt8ZHfpVs Rh5l3gI/ejn9s1AbxLUTU1/RPxRhH0hSOO2QENIg+FnGAUBW4e8+z8gKzd4/GaTGMGskfUHyqVR SmhNqM6RIjjH2O172p6erdVfFYyOU3y8gkWMU3Dn4YDBoUE2tk3NBs578WOrjgyXll3OqNDGzIt epfszATbbPUIQekAJXaWhNCA4iQ/MK6hExqBFgZD2bmoaQxduNL7PLfmeALJi+96IE9yuHoOCg5 v+8YL4yIsWvOH9ZnlIVovp4U2tA7BhHLMu/G/uuS7nidEou3j6bN+Uyqg81HCYdmdGT/2WkyRRG PB2oNNGkiy3kCw+S8+xoLyIJDwRTUE2ZhhCMfspPercI24g5UJ6cTbBgVbRYkeGVn9Vq8Y0yElK GH9cDz7oRXqpEGE/0tbdBrXhL9zKypqGSk4a5NbHpZKIwq+wJF2w== X-Received: by 2002:a05:600c:3542:b0:47e:e2b8:66e6 with SMTP id 5b1f17b1804b1-485198ee3admr278035e9.14.1772580354568; Tue, 03 Mar 2026 15:25:54 -0800 (PST) Received: from arch ([2a02:1210:2e28:2800:36a5:7f85:ccb8:1176]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4851335648esm68036615e9.5.2026.03.03.15.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2026 15:25:54 -0800 (PST) From: Gabriel Windlin To: Sudip Mukherjee , Teddy Wang , Greg Kroah-Hartman , linux-fbdev@vger.kernel.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Gabriel Windlin Subject: [PATCH 2/8] staging: sm750fb: remove unused CSC register definitions Date: Wed, 4 Mar 2026 00:24:23 +0100 Message-ID: <20260303232434.1850583-2-gawindlin@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260303232434.1850583-1-gawindlin@gmail.com> References: <20260303232434.1850583-1-gawindlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Color Space Conversion (CSC) register macros defined in ddk750_reg.h are not referenced anywhere in the driver. Remove them to reduce dead code as noted in the TODO file. Signed-off-by: Gabriel Windlin --- drivers/staging/sm750fb/ddk750_reg.h | 79 ---------------------------- 1 file changed, 79 deletions(-) diff --git a/drivers/staging/sm750fb/ddk750_reg.h b/drivers/staging/sm750fb/ddk750_reg.h index 59ecbc0d48f7..13b04870ad9b 100644 --- a/drivers/staging/sm750fb/ddk750_reg.h +++ b/drivers/staging/sm750fb/ddk750_reg.h @@ -1126,85 +1126,6 @@ /* Panel Palette register starts at 0x080C00 ~ 0x080FFC */ #define CRT_PALETTE_RAM 0x080C00 -/* Color Space Conversion registers. */ - -#define CSC_Y_SOURCE_BASE 0x1000C8 -#define CSC_Y_SOURCE_BASE_EXT BIT(27) -#define CSC_Y_SOURCE_BASE_CS BIT(26) -#define CSC_Y_SOURCE_BASE_ADDRESS_MASK 0x3ffffff - -#define CSC_CONSTANTS 0x1000CC -#define CSC_CONSTANTS_Y_MASK (0xff << 24) -#define CSC_CONSTANTS_R_MASK (0xff << 16) -#define CSC_CONSTANTS_G_MASK (0xff << 8) -#define CSC_CONSTANTS_B_MASK 0xff - -#define CSC_Y_SOURCE_X 0x1000D0 -#define CSC_Y_SOURCE_X_INTEGER_MASK (0x7ff << 16) -#define CSC_Y_SOURCE_X_FRACTION_MASK (0x1fff << 3) - -#define CSC_Y_SOURCE_Y 0x1000D4 -#define CSC_Y_SOURCE_Y_INTEGER_MASK (0xfff << 16) -#define CSC_Y_SOURCE_Y_FRACTION_MASK (0x1fff << 3) - -#define CSC_U_SOURCE_BASE 0x1000D8 -#define CSC_U_SOURCE_BASE_EXT BIT(27) -#define CSC_U_SOURCE_BASE_CS BIT(26) -#define CSC_U_SOURCE_BASE_ADDRESS_MASK 0x3ffffff - -#define CSC_V_SOURCE_BASE 0x1000DC -#define CSC_V_SOURCE_BASE_EXT BIT(27) -#define CSC_V_SOURCE_BASE_CS BIT(26) -#define CSC_V_SOURCE_BASE_ADDRESS_MASK 0x3ffffff - -#define CSC_SOURCE_DIMENSION 0x1000E0 -#define CSC_SOURCE_DIMENSION_X_MASK (0xffff << 16) -#define CSC_SOURCE_DIMENSION_Y_MASK 0xffff - -#define CSC_SOURCE_PITCH 0x1000E4 -#define CSC_SOURCE_PITCH_Y_MASK (0xffff << 16) -#define CSC_SOURCE_PITCH_UV_MASK 0xffff - -#define CSC_DESTINATION 0x1000E8 -#define CSC_DESTINATION_WRAP BIT(31) -#define CSC_DESTINATION_X_MASK (0xfff << 16) -#define CSC_DESTINATION_Y_MASK 0xfff - -#define CSC_DESTINATION_DIMENSION 0x1000EC -#define CSC_DESTINATION_DIMENSION_X_MASK (0xffff << 16) -#define CSC_DESTINATION_DIMENSION_Y_MASK 0xffff - -#define CSC_DESTINATION_PITCH 0x1000F0 -#define CSC_DESTINATION_PITCH_X_MASK (0xffff << 16) -#define CSC_DESTINATION_PITCH_Y_MASK 0xffff - -#define CSC_SCALE_FACTOR 0x1000F4 -#define CSC_SCALE_FACTOR_HORIZONTAL_MASK (0xffff << 16) -#define CSC_SCALE_FACTOR_VERTICAL_MASK 0xffff - -#define CSC_DESTINATION_BASE 0x1000F8 -#define CSC_DESTINATION_BASE_EXT BIT(27) -#define CSC_DESTINATION_BASE_CS BIT(26) -#define CSC_DESTINATION_BASE_ADDRESS_MASK 0x3ffffff - -#define CSC_CONTROL 0x1000FC -#define CSC_CONTROL_STATUS BIT(31) -#define CSC_CONTROL_SOURCE_FORMAT_MASK (0x7 << 28) -#define CSC_CONTROL_SOURCE_FORMAT_YUV422 (0x0 << 28) -#define CSC_CONTROL_SOURCE_FORMAT_YUV420I (0x1 << 28) -#define CSC_CONTROL_SOURCE_FORMAT_YUV420 (0x2 << 28) -#define CSC_CONTROL_SOURCE_FORMAT_YVU9 (0x3 << 28) -#define CSC_CONTROL_SOURCE_FORMAT_IYU1 (0x4 << 28) -#define CSC_CONTROL_SOURCE_FORMAT_IYU2 (0x5 << 28) -#define CSC_CONTROL_SOURCE_FORMAT_RGB565 (0x6 << 28) -#define CSC_CONTROL_SOURCE_FORMAT_RGB8888 (0x7 << 28) -#define CSC_CONTROL_DESTINATION_FORMAT_MASK (0x3 << 26) -#define CSC_CONTROL_DESTINATION_FORMAT_RGB565 (0x0 << 26) -#define CSC_CONTROL_DESTINATION_FORMAT_RGB8888 (0x1 << 26) -#define CSC_CONTROL_HORIZONTAL_FILTER BIT(25) -#define CSC_CONTROL_VERTICAL_FILTER BIT(24) -#define CSC_CONTROL_BYTE_ORDER BIT(23) - #define DE_DATA_PORT 0x110000 #define I2C_BYTE_COUNT 0x010040 -- 2.53.0