From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7225A3491F4 for ; Tue, 3 Mar 2026 23:25:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772580360; cv=none; b=RN1MtEU2Njv53kUIMENWMsUZLOlVvMCJdUawUkJude+UEedz0LoUabYzRMlkr/YjY5don1u1CfyLoU8mN5RMHLMPKu8HpiKu9iIHo7S+D7oeaulzQo+6AlkKYtCGOetZ3WGXZgzx7smpOQ6wJlKhBtDgKW3MKuoboIfHzplYt+k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772580360; c=relaxed/simple; bh=DZL51npHETrQOaLm+gXQSMAWjDCRqz6RGYaVU3tGRew=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Io5uZUlqZ02BDKVlmzonFZQXrh7FYB9U7f6XOB9jcomxThPsnZix1komb7GzyNgd1LlyqDB/IU7tq/KWGVCoYNYhR746utHgUoGbAhFW2tIF2zko5dakjKFjYDyyfHs4r3rsLHbx2zQNCvsV7vIc0sEgBxhDT+DF4jtRbjRMQgI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=P7uyK10v; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="P7uyK10v" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4837584120eso45668035e9.1 for ; Tue, 03 Mar 2026 15:25:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1772580356; x=1773185156; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q62znnvOqEzZPobsTXXdYeKA44XpPeuRQCLKUu1n+U0=; b=P7uyK10v6Kt8Ig+Xxo8KO7Wgtipf72spDpNTGd6d3QEr3mNKL+69YsByIOE2mi408g IKLtU1JM6RwWFhhVOjv2pvANDq88AKEl+8wPvISsTf3bkvpCMzovgRybKkbEX0RFwSud cad/J7LPnnyRkw6wXnMPRDb09lfeQEVrl+djDbRfs9jalsCfVAlc1SaoP5GCL/JExbjY 2D7ad/30ccShYY7VvbcFWX9Es7uQU+9LdsJ6x891G71JOUmkbzkrE5Rhsczfp07PH71F wb30axG051vd2Lp7Zw/9xELkqK3cw6/eEOMLzUGvh3wnYiwDyxCZfiXxvJKzK4QFEchC tVDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772580356; x=1773185156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=q62znnvOqEzZPobsTXXdYeKA44XpPeuRQCLKUu1n+U0=; b=Q5Q5dU//111XMOzVPy6Tnbrq7M881mRWpcf/ZI4/7k+f1o72fcAou0ZHmBWy8vXDOL 4ZoL6G/cf8CRPgqZiX8O6NxLkB/K7d9xmuM95UnFaQWWRU1uhP77NHEiwPPg8MvfEDqM EtYs8whWbtu6hVtD8bVPbc23vKIASwQdg34ve5BOml/NmDynjCm58/67rPLokE6fx3Mf raOW/BgsGzyljJ8zpXcTAXjHQ+Ft678aH2WkPi2nR6iNrZiTvIACTppRQhM4CwZe6xoj CtK1Qb/ifyr7XQ58jsjwW7elbsl6roC5mofp0/IUejbqvo5NPz09vTcFIdEESgBZlBRy jJGw== X-Forwarded-Encrypted: i=1; AJvYcCUCy8K9dE0yWOfOBsgUEHwnK1wHjAltsLJTJ/11/7dgXxOwPHsAd/NOqRGt1P6VbDe3pPdIirXSi2VPAQQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzjcdLeaFff/sarbUinOrCEKa104mzqL+qSv/c1aTNFuxaHb2fn cUXbcYhBQUWwK1brcTDlyFbxCnPvq2MRIqNeGgy4jvpjYxvDJKRu0B3y X-Gm-Gg: ATEYQzwDLV61BEYUCa0Oi7t0M2w1LgGhajWt7FGaakVMgcI4/JqGv9Ugvz1eCQSct0D W/LBVMbfGTxjze4unHBAO3FHXUwuPipJ7LGOheGnGdClAFBtzULfhOmd1CVqX36itKeYR1l7xST riCiYRAnf/0AbjG5eTi/3yAC5pmn5UWthEHacz283r3JFgwNCds6M2sxBOgO9vvwzasM5j8JZCx YgdhnI3lHwIhr2K1kIMbJ0fx7dsjV7gFiWo/Sf1yqdif+X7C+rKVJZJUTt6mh6FpMMIO5Cla1nw Qp1fRoJiAv5vz7adngTSDqgToNRnIWHWwpEWLKs9zSbMdjLkY1/15s7WPCMQqPJz2cHuVayBYcH 5lym5aM9yoH1smhxNQjedDK2wQkiiDOtv0djUBQrbtx/DHe2aTKiWsSMNHwB9My5kS6anNR8Zjc rOcQ0aNo7Hj/bbeGuLgo4796k/QO92zQIsCQKb9OHvtxjIuMGfu4BYcFrxUWWt X-Received: by 2002:a05:600c:1d05:b0:483:badb:618f with SMTP id 5b1f17b1804b1-48519887d35mr606095e9.25.1772580355798; Tue, 03 Mar 2026 15:25:55 -0800 (PST) Received: from arch ([2a02:1210:2e28:2800:36a5:7f85:ccb8:1176]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4851335648esm68036615e9.5.2026.03.03.15.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2026 15:25:55 -0800 (PST) From: Gabriel Windlin To: Sudip Mukherjee , Teddy Wang , Greg Kroah-Hartman , linux-fbdev@vger.kernel.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Cc: Gabriel Windlin Subject: [PATCH 3/8] staging: sm750fb: remove unused ZV capture register definitions Date: Wed, 4 Mar 2026 00:24:24 +0100 Message-ID: <20260303232434.1850583-3-gawindlin@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260303232434.1850583-1-gawindlin@gmail.com> References: <20260303232434.1850583-1-gawindlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The ZV0 and ZV1 video capture port register macros defined in ddk750_reg.h are not referenced anywhere in the driver. Remove them to reduce dead code as noted in the TODO file. Signed-off-by: Gabriel Windlin --- drivers/staging/sm750fb/ddk750_reg.h | 141 --------------------------- 1 file changed, 141 deletions(-) diff --git a/drivers/staging/sm750fb/ddk750_reg.h b/drivers/staging/sm750fb/ddk750_reg.h index 13b04870ad9b..efdafa993e86 100644 --- a/drivers/staging/sm750fb/ddk750_reg.h +++ b/drivers/staging/sm750fb/ddk750_reg.h @@ -1168,147 +1168,6 @@ #define I2C_DATA14 0x010052 #define I2C_DATA15 0x010053 -#define ZV0_CAPTURE_CTRL 0x090000 -#define ZV0_CAPTURE_CTRL_FIELD_INPUT BIT(27) -#define ZV0_CAPTURE_CTRL_SCAN BIT(26) -#define ZV0_CAPTURE_CTRL_CURRENT_BUFFER BIT(25) -#define ZV0_CAPTURE_CTRL_VERTICAL_SYNC BIT(24) -#define ZV0_CAPTURE_CTRL_ADJ BIT(19) -#define ZV0_CAPTURE_CTRL_HA BIT(18) -#define ZV0_CAPTURE_CTRL_VSK BIT(17) -#define ZV0_CAPTURE_CTRL_HSK BIT(16) -#define ZV0_CAPTURE_CTRL_FD BIT(15) -#define ZV0_CAPTURE_CTRL_VP BIT(14) -#define ZV0_CAPTURE_CTRL_HP BIT(13) -#define ZV0_CAPTURE_CTRL_CP BIT(12) -#define ZV0_CAPTURE_CTRL_UVS BIT(11) -#define ZV0_CAPTURE_CTRL_BS BIT(10) -#define ZV0_CAPTURE_CTRL_CS BIT(9) -#define ZV0_CAPTURE_CTRL_CF BIT(8) -#define ZV0_CAPTURE_CTRL_FS BIT(7) -#define ZV0_CAPTURE_CTRL_WEAVE BIT(6) -#define ZV0_CAPTURE_CTRL_BOB BIT(5) -#define ZV0_CAPTURE_CTRL_DB BIT(4) -#define ZV0_CAPTURE_CTRL_CC BIT(3) -#define ZV0_CAPTURE_CTRL_RGB BIT(2) -#define ZV0_CAPTURE_CTRL_656 BIT(1) -#define ZV0_CAPTURE_CTRL_CAP BIT(0) - -#define ZV0_CAPTURE_CLIP 0x090004 -#define ZV0_CAPTURE_CLIP_EYCLIP_MASK (0x3ff << 16) -#define ZV0_CAPTURE_CLIP_XCLIP_MASK 0x3ff - -#define ZV0_CAPTURE_SIZE 0x090008 -#define ZV0_CAPTURE_SIZE_HEIGHT_MASK (0x7ff << 16) -#define ZV0_CAPTURE_SIZE_WIDTH_MASK 0x7ff - -#define ZV0_CAPTURE_BUF0_ADDRESS 0x09000C -#define ZV0_CAPTURE_BUF0_ADDRESS_STATUS BIT(31) -#define ZV0_CAPTURE_BUF0_ADDRESS_EXT BIT(27) -#define ZV0_CAPTURE_BUF0_ADDRESS_CS BIT(26) -#define ZV0_CAPTURE_BUF0_ADDRESS_ADDRESS_MASK 0x3ffffff - -#define ZV0_CAPTURE_BUF1_ADDRESS 0x090010 -#define ZV0_CAPTURE_BUF1_ADDRESS_STATUS BIT(31) -#define ZV0_CAPTURE_BUF1_ADDRESS_EXT BIT(27) -#define ZV0_CAPTURE_BUF1_ADDRESS_CS BIT(26) -#define ZV0_CAPTURE_BUF1_ADDRESS_ADDRESS_MASK 0x3ffffff - -#define ZV0_CAPTURE_BUF_OFFSET 0x090014 -#ifndef VALIDATION_CHIP - #define ZV0_CAPTURE_BUF_OFFSET_YCLIP_ODD_FIELD (0x3ff << 16) -#endif -#define ZV0_CAPTURE_BUF_OFFSET_OFFSET_MASK 0xffff - -#define ZV0_CAPTURE_FIFO_CTRL 0x090018 -#define ZV0_CAPTURE_FIFO_CTRL_FIFO_MASK 0x7 -#define ZV0_CAPTURE_FIFO_CTRL_FIFO_0 0 -#define ZV0_CAPTURE_FIFO_CTRL_FIFO_1 1 -#define ZV0_CAPTURE_FIFO_CTRL_FIFO_2 2 -#define ZV0_CAPTURE_FIFO_CTRL_FIFO_3 3 -#define ZV0_CAPTURE_FIFO_CTRL_FIFO_4 4 -#define ZV0_CAPTURE_FIFO_CTRL_FIFO_5 5 -#define ZV0_CAPTURE_FIFO_CTRL_FIFO_6 6 -#define ZV0_CAPTURE_FIFO_CTRL_FIFO_7 7 - -#define ZV0_CAPTURE_YRGB_CONST 0x09001C -#define ZV0_CAPTURE_YRGB_CONST_Y_MASK (0xff << 24) -#define ZV0_CAPTURE_YRGB_CONST_R_MASK (0xff << 16) -#define ZV0_CAPTURE_YRGB_CONST_G_MASK (0xff << 8) -#define ZV0_CAPTURE_YRGB_CONST_B_MASK 0xff - -#define ZV0_CAPTURE_LINE_COMP 0x090020 -#define ZV0_CAPTURE_LINE_COMP_LC_MASK 0x7ff - -/* ZV1 */ - -#define ZV1_CAPTURE_CTRL 0x098000 -#define ZV1_CAPTURE_CTRL_FIELD_INPUT BIT(27) -#define ZV1_CAPTURE_CTRL_SCAN BIT(26) -#define ZV1_CAPTURE_CTRL_CURRENT_BUFFER BIT(25) -#define ZV1_CAPTURE_CTRL_VERTICAL_SYNC BIT(24) -#define ZV1_CAPTURE_CTRL_PANEL BIT(20) -#define ZV1_CAPTURE_CTRL_ADJ BIT(19) -#define ZV1_CAPTURE_CTRL_HA BIT(18) -#define ZV1_CAPTURE_CTRL_VSK BIT(17) -#define ZV1_CAPTURE_CTRL_HSK BIT(16) -#define ZV1_CAPTURE_CTRL_FD BIT(15) -#define ZV1_CAPTURE_CTRL_VP BIT(14) -#define ZV1_CAPTURE_CTRL_HP BIT(13) -#define ZV1_CAPTURE_CTRL_CP BIT(12) -#define ZV1_CAPTURE_CTRL_UVS BIT(11) -#define ZV1_CAPTURE_CTRL_BS BIT(10) -#define ZV1_CAPTURE_CTRL_CS BIT(9) -#define ZV1_CAPTURE_CTRL_CF BIT(8) -#define ZV1_CAPTURE_CTRL_FS BIT(7) -#define ZV1_CAPTURE_CTRL_WEAVE BIT(6) -#define ZV1_CAPTURE_CTRL_BOB BIT(5) -#define ZV1_CAPTURE_CTRL_DB BIT(4) -#define ZV1_CAPTURE_CTRL_CC BIT(3) -#define ZV1_CAPTURE_CTRL_RGB BIT(2) -#define ZV1_CAPTURE_CTRL_656 BIT(1) -#define ZV1_CAPTURE_CTRL_CAP BIT(0) - -#define ZV1_CAPTURE_CLIP 0x098004 -#define ZV1_CAPTURE_CLIP_YCLIP_MASK (0x3ff << 16) -#define ZV1_CAPTURE_CLIP_XCLIP_MASK 0x3ff - -#define ZV1_CAPTURE_SIZE 0x098008 -#define ZV1_CAPTURE_SIZE_HEIGHT_MASK (0x7ff << 16) -#define ZV1_CAPTURE_SIZE_WIDTH_MASK 0x7ff - -#define ZV1_CAPTURE_BUF0_ADDRESS 0x09800C -#define ZV1_CAPTURE_BUF0_ADDRESS_STATUS BIT(31) -#define ZV1_CAPTURE_BUF0_ADDRESS_EXT BIT(27) -#define ZV1_CAPTURE_BUF0_ADDRESS_CS BIT(26) -#define ZV1_CAPTURE_BUF0_ADDRESS_ADDRESS_MASK 0x3ffffff - -#define ZV1_CAPTURE_BUF1_ADDRESS 0x098010 -#define ZV1_CAPTURE_BUF1_ADDRESS_STATUS BIT(31) -#define ZV1_CAPTURE_BUF1_ADDRESS_EXT BIT(27) -#define ZV1_CAPTURE_BUF1_ADDRESS_CS BIT(26) -#define ZV1_CAPTURE_BUF1_ADDRESS_ADDRESS_MASK 0x3ffffff - -#define ZV1_CAPTURE_BUF_OFFSET 0x098014 -#define ZV1_CAPTURE_BUF_OFFSET_OFFSET_MASK 0xffff - -#define ZV1_CAPTURE_FIFO_CTRL 0x098018 -#define ZV1_CAPTURE_FIFO_CTRL_FIFO_MASK 0x7 -#define ZV1_CAPTURE_FIFO_CTRL_FIFO_0 0 -#define ZV1_CAPTURE_FIFO_CTRL_FIFO_1 1 -#define ZV1_CAPTURE_FIFO_CTRL_FIFO_2 2 -#define ZV1_CAPTURE_FIFO_CTRL_FIFO_3 3 -#define ZV1_CAPTURE_FIFO_CTRL_FIFO_4 4 -#define ZV1_CAPTURE_FIFO_CTRL_FIFO_5 5 -#define ZV1_CAPTURE_FIFO_CTRL_FIFO_6 6 -#define ZV1_CAPTURE_FIFO_CTRL_FIFO_7 7 - -#define ZV1_CAPTURE_YRGB_CONST 0x09801C -#define ZV1_CAPTURE_YRGB_CONST_Y_MASK (0xff << 24) -#define ZV1_CAPTURE_YRGB_CONST_R_MASK (0xff << 16) -#define ZV1_CAPTURE_YRGB_CONST_G_MASK (0xff << 8) -#define ZV1_CAPTURE_YRGB_CONST_B_MASK 0xff - #define DMA_1_SOURCE 0x0D0010 #define DMA_1_SOURCE_ADDRESS_EXT BIT(27) #define DMA_1_SOURCE_ADDRESS_CS BIT(26) -- 2.53.0