From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28B8838E133; Fri, 6 Mar 2026 14:09:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772806191; cv=none; b=oBz9/5ZX1fuENVvZyEovGcI2heyr9FQPatNMjFghZMEbPA2nbOJj9pBJDd1VpFaPuB12J/MiUY1x9cOkWwElFS4jwm4QNss9Hi3RxVIjgfzXAzPdS24q7GHlLgK0ZW6//6Hnmcmz8JEN7/lkn58t4K/Acecg0AgeFbXW+tVBKAc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772806191; c=relaxed/simple; bh=QAEkleb6IVGK5L78+HXxLeZCePSBUtX84+LuF5RCLcQ=; h=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc; b=cL+UXFJfd1N/TrCkWFeyzh4Tr7VaK+2jRF199mvjLDHZOAabFdUDgEUFhwMznIoPVUDH7+AGylWAmcdTj0FOFBow81TYoKHpYIl89Cu0j7BpWMET+nFvU5WaEGyStEhZmdVCjcT06+RY+vM5VOqlH7kcANKV+9PK+cpp+xfrBoI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IQRlj30T; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IQRlj30T" Received: by smtp.kernel.org (Postfix) with ESMTPS id C063EC4CEF7; Fri, 6 Mar 2026 14:09:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772806190; bh=QAEkleb6IVGK5L78+HXxLeZCePSBUtX84+LuF5RCLcQ=; h=From:Subject:Date:To:Cc:Reply-To:From; b=IQRlj30TaF5FwIKhWPfQrnBwYLtspSXKjdkakMyqSka9OqdS+2ziLg8DEAc3Y1Hoy dDLYOQ7AQgI3SAVtzdZeTW/C5e2Z3gLgyJfk1sA+pr55R9TXDcaVR+WWOLGoLp4hp7 5Lyy12R6EcxInUYa5TbTI1OQaPjJ19MttN8zCMjlxDhUx5qPOH+S2ysSXlWQCY9j9q QOeWn48T2O2DCKbDpsZCK6XVLG58+p7geej/6cVLM2pVY1/sccY4ciPgCYPtmAuq6r IvkwCpvJv3XTlyR02IsaDxWkfKzp6IMEE1CTRNHroYL3KUEQmBOJ/GQJdZDYdUcN1Z NLTvPdJ0+Hpeg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD5DFF0181F; Fri, 6 Mar 2026 14:09:50 +0000 (UTC) From: Michael Riesch via B4 Relay Subject: [PATCH 0/4] media: synopsys: csi2rx: add support for rk3588 variant Date: Fri, 06 Mar 2026 15:09:47 +0100 Message-Id: <20260305-rk3588-csi2rx-v1-0-0cd8d2bf28c0@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIACvgqmkC/x2NQQqDQAwAvyI5N7C7uir9SukhbmMNlW1JaBHEv zd4nIFhdjBWYYNrs4PyT0ze1SFeGigL1SejPJwhhdSHNmTUV5vHEYtJ0g0pxnkoMVMXCLyZyBg npVoWr+p3XV1+lGfZzsntfhx/AsxoBXQAAAA= To: Mauro Carvalho Chehab , Sakari Ailus , Laurent Pinchart , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Kever Yang , Collabora Kernel Team Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Michael Riesch X-Mailer: b4 0.12.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1772806189; l=2252; i=michael.riesch@collabora.com; s=20250410; h=from:subject:message-id; bh=QAEkleb6IVGK5L78+HXxLeZCePSBUtX84+LuF5RCLcQ=; b=+z1lAM+K34CYNMrpDG4Vre36ujGjSJtdNTMfHFjGBxHcLTuD65Qq7K+Px6e8p2q3OwnGFIp62 NqLrn7qvsTHBOWIwzloMo39o8x8PtoJjfJAz4fBU1hvQX/HBnS8oizi X-Developer-Key: i=michael.riesch@collabora.com; a=ed25519; pk=+MWX1fffLFZtTPG/I6XdYm/+OSvpRE8D9evQaWbiN04= X-Endpoint-Received: by B4 Relay for michael.riesch@collabora.com/20250410 with auth_id=371 X-Original-From: Michael Riesch Reply-To: michael.riesch@collabora.com Habidere, The Rockchip RK3588 features six MIPI CSI-2 receiver units: - MIPI0: connected to MIPI DCPHY0 - MIPI1: connected to MIPI DCPHY1 - MIPI2: connected to MIPI DPHY0 - MIPI3: connected to MIPI DPHY0-1 (only with split DPHY0) - MIPI4: connected to MIPI DPHY1 - MIPI5: connected to MIPI DPHY1-1 (only with split DPHY1) The MIPI DCPHYs (at least the CSI-2 features of them) as well as the split DPHY mode of the DPHYs are not yet supported by mainline. However, we can already provide support for the MIPI2 and MIPI4 units. When support for the split DPHY mode is introduced, the DPHY nodes should have the property #phy-cells = <1>; and the MIPI CSI-2 receiver nodes should have the property phys = <&csi_dphy{0,1} {0,1}>; in case the split mode is desired. Since this is a board specific hardware design, the properties need to be changed in the board device tree (or any overlays). As reasonable default, however, we can define, e.g., #phy-cells = <0>; and phys = <&csi_dphy{0,1}>; in the SoC device tree include. This series introduces initial support for this default configuration. In a related note, the split DPHY allows for different integrations of the MIPI CSI-2 receiver into the different SoCs. Therefore, we introduce a separate compatible (and not only a fallback compatible) in the DT bindings. Looking forward to your comments! Signed-off-by: Michael Riesch --- Michael Riesch (4): media: dt-bindings: rockchip,rk3568-mipi-csi2: add rk3588 compatible media: synopsys: csi2rx: add support for rk3588 variant arm64: dts: rockchip: add mipi csi-2 receiver nodes to rk3588 arm64: defconfig: enable designware mipi csi-2 receiver .../bindings/media/rockchip,rk3568-mipi-csi2.yaml | 1 + arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 52 ++++++++++++++++++++++ arch/arm64/configs/defconfig | 1 + drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 3 ++ 4 files changed, 57 insertions(+) --- base-commit: 11439c4635edd669ae435eec308f4ab8a0804808 change-id: 20260305-rk3588-csi2rx-a11f7c15a40a Best regards, -- Michael Riesch