[PATCH 2/2] x86/cpu/intel: Add EIST workaround for Lightning Mountain.

[Martin Schiller <ms@dev.tdt.de>]

Add a workaround for Intel / MaxLinear Lightning Mountain to enable
Enhanced Intel SpeedStep Technology (EIST) for each cpu. Otherwise, the
frequency on some cpus is locked to the minimum value of 624 MHz.
This usually would be the job of the BIOS / bootloader, but U-Boot only
enables it on the cpu on which it is running.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
---
 arch/x86/kernel/cpu/intel.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 98ae4c37c93eccf775d5632acf122603a19918a8..e49df04e8d491158cc48f8d8bef824c434256d09 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -466,6 +466,29 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
 #else
 static void intel_workarounds(struct cpuinfo_x86 *c)
 {
+	u64 misc_enable;
+
+	/*
+	 * Intel / MaxLinear Lightning Mountain workaround to enable Enhanced
+	 * Intel SpeedStep Technology (EIST) for each cpu. Otherwise, the
+	 * frequency on some cpus is locked to the minimum value of 624 MHz.
+	 * This usually would be the job of the BIOS / bootloader, but U-Boot
+	 * only enables it on the cpu on which it is running.
+	 */
+	if (c->x86_vfm == INTEL_ATOM_AIRMONT_NP) {
+		rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable);
+		if (!(misc_enable & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
+			misc_enable |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
+			wrmsrq(MSR_IA32_MISC_ENABLE, misc_enable);
+
+			/* check to see if it was enabled successfully */
+			rdmsrq(MSR_IA32_MISC_ENABLE, misc_enable);
+			if (!(misc_enable & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
+				pr_info("CPU%d: Can't enable Enhanced SpeedStep\n",
+					c->cpu_index);
+			}
+		}
+	}
 }
 #endif
 

-- 
2.47.3