From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F30D135838C for ; Mon, 9 Mar 2026 07:32:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773041556; cv=none; b=PbExIkNIXA3EVrz0/B0LfzBqF9TEIBbDg7GOrF1uX+UF0JCivmLtoFJJkBoqyyQussC8w/b3b8VAtZPdsBx53u4igVvA8m6YHYKel5ROnGWWh/mT+U6v6xDk6cDnlrv1oxMnfrbY7R9E09UEBq1C3q4vNkJ1ql7e1JfC/zDBTHk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773041556; c=relaxed/simple; bh=VauP1ROV92pNMZ/iiYucSS+d65dDT5JM4Zbi/ebIsaY=; h=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc; b=eWUUPoOi6PFiG/590odPuUtxeQd57pzucFt8/odvfQm6f+SLCSNCTdTRQM9Xs4LOUpEo+8vNJQ3sYKxM9Dhx34zlZmRHRT1HFtnnVjtrXdfC+gz4uYRVaKq3sm6+m6/6KuEz03Ui6z1YfRYeBMoLIc4r27JzKKzK3zVkLpt3loM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=O+ZVlLKb; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="O+ZVlLKb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773041553; x=1804577553; h=from:subject:date:message-id:mime-version: content-transfer-encoding:to:cc; bh=VauP1ROV92pNMZ/iiYucSS+d65dDT5JM4Zbi/ebIsaY=; b=O+ZVlLKbxigowyJqithF23Gt8vj4bJsNqq+76OLaDirYAfPMJmT+vC36 0BRNttev0kTRkg6OnMcYkE4IsYTP4u9PjmWm98OnilQnz8R69OivZNPA5 +P1P5n/eav0buxa/k4DRSqrY/9FCUiwM/O8BqCFwjO6kAB7ngUn7Hzx4Z BafzTdi/XlW0RqSXgCvVx9JqRzcEWuoIHnWN29fLPg+npzNXmHUFmj+E3 foiWbcapbyIGibj1lMAyt8+SEBnnJXyJ6fmCJAo/j4DlAw7IeSJrI/JiK FFhPhRcr72/U9Ym7C7Ya+mVrKV51Gw0uo1WYZQgdAvZtYnlOQ6pSm7clM A==; X-CSE-ConnectionGUID: gFaL0dnTQ1OfD+et+warBg== X-CSE-MsgGUID: t6s9smGOT1qeYr9miOJQjw== X-IronPort-AV: E=McAfee;i="6800,10657,11723"; a="77935629" X-IronPort-AV: E=Sophos;i="6.23,109,1770624000"; d="scan'208";a="77935629" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Mar 2026 00:31:01 -0700 X-CSE-ConnectionGUID: KGrwCQIyT+OAq4NdDxzGsw== X-CSE-MsgGUID: fGf5GSr+TVmxPWcb6SulNA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,109,1770624000"; d="scan'208";a="217286703" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by fmviesa007.fm.intel.com with ESMTP; 09 Mar 2026 00:30:58 -0700 From: Arun R Murthy Subject: [PATCH RFC 0/3] Some updates over DP AUX Transactions Date: Mon, 09 Mar 2026 12:59:23 +0530 Message-Id: <20260309-dp_aux_timeout-v1-0-08c610a63a84@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIANN2rmkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDYwNL3ZSC+MTSiviSzNzU/NISXcsU0yTDJGPTRIMUCyWgpoKi1LTMCrC B0UpBbs5KsbW1AJR6yNFlAAAA X-Change-ID: 20260309-dp_aux_timeout-9d5b1b35a0d8 To: Simona Vetter , Jani Nikula , ville.syrjala@linux.intel.com, suraj.kandpal@intel.com, imre.deak@intel.com Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Arun R Murthy X-Mailer: b4 0.15-dev Based on the discussions/comments on the patch https://lore.kernel.org/intel-xe/aaVWbdt1vOFxGAb1@ideak-desk.lan/ in order to address the real HW(DPTX) generated timeout and adress the fix, this series is targetted. Along with this it was noticed that the the AUX power request bit in the port control register is being touched outside the power well framework. The limitation due to the way aux port control register was programmed. Replacing the aux control register write to read/mask/write thereby writing only the required bits. Note: This is RFC and full round of testing the pending. Signed-off-by: Arun R Murthy --- Arun R Murthy (3): drm/display/dp: Export function to wake the sink AUX_CH drm/i915/dp: On AUX_CH tx timeout, wake up the sink drm/i915/dp: Configure PORT_AUX_CTL and then trigger the tx drivers/gpu/drm/display/drm_dp_helper.c | 36 +++++++++ drivers/gpu/drm/i915/display/intel_display_types.h | 6 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 94 +++++++++++++++------- drivers/gpu/drm/i915/display/intel_psr.c | 29 ++++--- include/drm/display/drm_dp_helper.h | 1 + 5 files changed, 123 insertions(+), 43 deletions(-) --- base-commit: 6884fe03ff2bc5a2f501ba4710f950dd4933ac84 change-id: 20260309-dp_aux_timeout-9d5b1b35a0d8 Best regards, -- Arun R Murthy