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[67.164.93.214]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2be4f948631sm7240105eec.19.2026.03.08.17.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Mar 2026 17:45:32 -0700 (PDT) From: Sanman Pradhan To: Sanman Pradhan , Guenter Roeck Cc: Sanman Pradhan , linux-hwmon , linux-kernel Subject: [PATCH v2 0/2] hwmon: (pmbus/max31785) refactor inter-access delay Date: Sun, 8 Mar 2026 17:45:06 -0700 Message-Id: <20260309004508.78609-1-sanman.p211993@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Sanman Pradhan Thanks for applying Patch 1 from the previous series. This v2 series addresses the feedback regarding the raw i2c_transfer() error path in the MAX31785 driver. Instead of relying on local usleep_range() calls, this series exports the PMBus core timing helpers so the driver can utilize the core's delay management. Changes in v2: - Dropped the i2c_smbus_write_byte_data() wrapper cleanup (applied upstream). - Patch 1 (New): Export pmbus_wait() and pmbus_update_ts() from the PMBus core, and move PMBUS_OP_* macros to drivers/hwmon/pmbus/pmbus.h. - Patch 2: Replaced the usleep_range() sandwich in max31785_read_long_data() with the newly exported core timing functions. Placed pmbus_update_ts() before the error check to ensure the core accurately tracks the bus transaction even on failure. Sanman Pradhan (2): hwmon: (pmbus/core) export pmbus_wait and pmbus_update_ts hwmon: (pmbus/max31785) use access_delay for PMBus-mediated accesses drivers/hwmon/pmbus/max31785.c | 184 ++++++++++--------------------- drivers/hwmon/pmbus/pmbus.h | 9 ++ drivers/hwmon/pmbus/pmbus_core.c | 13 +-- 3 files changed, 70 insertions(+), 136 deletions(-) -- 2.34.1