From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from m16.mail.163.com (m16.mail.163.com [220.197.31.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3589B22D7B5 for ; Mon, 9 Mar 2026 02:22:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.2 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773022973; cv=none; b=RyusbOIhQZMm+XxRXK3dDMJVEogawmNVjHIYH0csGQAc8705ytUDAU7vTYv09SLdKwkicS28G5pvz8EBia4g7iR9yW3V+6leTWuen8IPN44xYjYDk5HZvEsxjYNEtjGdDBMxJF0miaSeuEGSeNLFeyiZAIZLztqZZ+Y0g7EC1a0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773022973; c=relaxed/simple; bh=8K7nRyOQP2w3jup8KTWj4An8jJ+zTpRWFd2G4m9mupE=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=PNM8mjSgIkodUYEEG2J87n4w5IqeZRqC5geO8zcmxx3eIteJzOmFrCrQODJmt0obDn6VuxKzGcIV6GegLyCbARbpP/frMGriq9D87KvnfO2F+xQlQbnAAdOVBOiaC2uHAu2NnLduuwMbdylsigO2dTzEticr3m5N1UFoXmK0vJQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com; spf=pass smtp.mailfrom=163.com; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b=Yo4U1JQE; arc=none smtp.client-ip=220.197.31.2 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=163.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=163.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=163.com header.i=@163.com header.b="Yo4U1JQE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=YM d0+Wp/o+zkTTLjkBVKHAkw64/YlBP0XcUPa1Rlkb4=; b=Yo4U1JQEoeAWln00la 9OwgDsyVQH3AH0G59asyOIfpWi5y/4Vnk+PiRjA3wgfeX5f2AefY5nYKcJ9CzMEk CH7/wD6vVhTsdnocXwfSeR0MpaTsk6p+APTlQeIKTKGRCyIQWNVcdr/CMbUOITn5 qcHL0zUcBTYaNMnL/r1p7VBJE= Received: from localhost.localdomain (unknown []) by gzga-smtp-mtada-g1-4 (Coremail) with SMTP id _____wDXV5TmLq5pRMZoPg--.11725S2; Mon, 09 Mar 2026 10:22:31 +0800 (CST) From: Chenyuan Mi To: alexander.deucher@amd.com, christian.koenig@amd.com Cc: Arunpravin.PaneerSelvam@amd.com, airlied@gmail.com, simona@ffwll.ch, amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/2] drm/amdgpu: fix use-after-free in userq signal/wait IOCTLs Date: Mon, 9 Mar 2026 10:22:27 +0800 Message-ID: <20260309022229.63071-1-chenyuan_mi@163.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:_____wDXV5TmLq5pRMZoPg--.11725S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7tF43Jry5Kr47GF45Ar1fJFb_yoW8GrWfpr 1rJw12kF4UXrn7Za47Ja48WFWkWFWfWFWfGF1xW34ru3W5X3Z8Zry8KFyrZrySkrs2ya9F qr1kX3y8JF1q93DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jaZX5UUUUU= X-CM-SenderInfo: xfkh055xdqszrl6rljoofrz/xtbC9gfK3WmuLuco0QAA3R Both amdgpu_userq_wait_ioctl() and amdgpu_userq_signal_ioctl() access user queue objects obtained from xa_load() without holding userq_mutex. A concurrent AMDGPU_USERQ_OP_FREE can destroy and kfree the queue in this window, leading to use-after-free. The two bugs have different origins: - Patch 1 fixes a wait-path regression introduced by commit 4b27406380b0 ("drm/amdgpu: Add queue id support to the user queue wait IOCTL"), which removed the indirect fence_drv_xa_ptr model and its NULL-check safety net from commit ed5fdc1fc282 ("drm/amdgpu: Fix the use-after-free issue in wait IOCTL"). - Patch 2 fixes a similar pre-existing lifetime bug in the signal path, present since commit a292fdecd728 ("drm/amdgpu: Implement userqueue signal/wait IOCTL"). Patch 1 adds explicit userq_mutex coverage around the xa_load and subsequent fence_drv_xa operations in the wait path. Patch 2 moves the ensure_ev_fence call (which acquires userq_mutex) before xa_load in the signal path, so that the queue lookup and all subsequent accesses are covered by the same lock. Chenyuan Mi (2): drm/amdgpu: protect waitq access with userq_mutex in wait IOCTL drm/amdgpu: protect queue access in signal IOCTL .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 25 +++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) -- 2.53.0