From: Caleb James DeLisle <cjd@cjdns.fr>
To: linux-mips@vger.kernel.org
Cc: naseefkm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
cjd@cjdns.fr, tsbogend@alpha.franken.de, ryder.lee@mediatek.com,
jianjun.wang@mediatek.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, bhelgaas@google.com,
vkoul@kernel.org, neil.armstrong@linaro.org,
p.zabel@pengutronix.de, matthias.bgg@gmail.com,
angelogioacchino.delregno@collabora.com, nbd@nbd.name,
ansuelsmth@gmail.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 3/8] dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528
Date: Mon, 9 Mar 2026 13:18:13 +0000 [thread overview]
Message-ID: <20260309131818.74467-4-cjd@cjdns.fr> (raw)
In-Reply-To: <20260309131818.74467-1-cjd@cjdns.fr>
EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY
which behaves slightly differently because one slot is Gen1/Gen2 while
the other is Gen1 only.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
.../phy/econet,en751221-pcie-phy.yaml | 50 +++++++++++++++++++
MAINTAINERS | 6 +++
2 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
new file mode 100644
index 000000000000..987d396c1c64
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528
+
+maintainers:
+ - Caleb James DeLisle <cjd@cjdns.fr>
+
+description:
+ The PCIe PHY supports physical layer functionality for PCIe Gen1 and
+ Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while
+ port 1 is Gen1/Gen2 capable.
+
+properties:
+ compatible:
+ enum:
+ - econet,en751221-pcie-gen1
+ - econet,en751221-pcie-gen2
+ - econet,en7528-pcie-gen1
+ - econet,en7528-pcie-gen2
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pcie-phy@1faf2000 {
+ compatible = "econet,en7528-pcie-gen1";
+ reg = <0x1faf2000 0x1000>;
+ #phy-cells = <0>;
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 3781d55db5bb..bc925fa08baa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9122,6 +9122,12 @@ F: drivers/irqchip/irq-econet-en751221.c
F: include/dt-bindings/clock/econet,en751221-scu.h
F: include/dt-bindings/reset/econet,en751221-scu.h
+ECONET PCIE PHY DRIVER
+M: Caleb James DeLisle <cjd@cjdns.fr>
+L: linux-mips@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
+
ECRYPT FILE SYSTEM
M: Tyler Hicks <code@tyhicks.com>
L: ecryptfs@vger.kernel.org
--
2.39.5
next prev parent reply other threads:[~2026-03-09 13:18 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-09 13:18 [PATCH v2 0/8] mips: econet: Add clk/reset and PCIe support Caleb James DeLisle
2026-03-09 13:18 ` [PATCH v2 1/8] dt-bindings: clock, reset: Add econet EN751221 Caleb James DeLisle
2026-03-10 8:21 ` Krzysztof Kozlowski
2026-03-10 8:37 ` Caleb James DeLisle
2026-03-10 8:51 ` Krzysztof Kozlowski
2026-03-09 13:18 ` [PATCH v2 2/8] clk: airoha: Add econet EN751221 clock/reset support to en7523-scu Caleb James DeLisle
2026-03-11 14:39 ` Brian Masney
2026-03-11 17:12 ` Caleb James DeLisle
2026-03-11 19:44 ` Brian Masney
2026-03-09 13:18 ` Caleb James DeLisle [this message]
2026-03-10 8:24 ` [PATCH v2 3/8] dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528 Krzysztof Kozlowski
2026-03-10 10:37 ` Caleb James DeLisle
2026-03-10 10:40 ` Krzysztof Kozlowski
2026-03-10 10:40 ` Krzysztof Kozlowski
2026-03-10 11:13 ` Caleb James DeLisle
2026-03-10 11:20 ` Krzysztof Kozlowski
2026-03-09 13:18 ` [PATCH v2 4/8] phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs Caleb James DeLisle
2026-03-09 13:18 ` [PATCH v2 5/8] dt-bindings: PCI: mediatek: Add support for EcoNet EN7528 Caleb James DeLisle
2026-03-10 8:25 ` Krzysztof Kozlowski
2026-03-10 8:49 ` Caleb James DeLisle
2026-03-09 13:18 ` [PATCH v2 6/8] PCI: mediatek: Add support for EcoNet EN7528 SoC Caleb James DeLisle
2026-03-09 13:18 ` [PATCH v2 7/8] PCI: Skip bridge window reads when window is not supported Caleb James DeLisle
2026-03-09 13:18 ` [PATCH v2 8/8] mips: dts: Add PCIe to EcoNet EN751221 Caleb James DeLisle
2026-04-06 12:37 ` Thomas Bogendoerfer
2026-04-08 12:58 ` Caleb James DeLisle
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