From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 101622BD11 for ; Tue, 10 Mar 2026 00:53:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773104029; cv=none; b=UEKLJHjyYiHn2eu9KR06k7XaCRd3F+9EZ4/7j24xTzzjnAE8tUL8bmhXGeizY8MMiv+rcTPYbMDecvB3k7yjaEsX6e5T1MYTt62NCsDqlt9V3d9q1RjrRsKHetoEdVLLlATLBhCUAmt511E1T6foNkED3oBHGWOsgHQ2JEsXrbc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773104029; c=relaxed/simple; bh=DvI49Q1USPoz7sbq6fRY8R9q3JqgFur1VEVLCWHrz1s=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=mkwP2LKezyZlFIl9QGERGxOzVo7a1OtBdrb/MpEFxa0XLODdJeKcz0dH91MjVDoXYwDsAt+JG4Cz1L2hgUd+UQAs75OKRk7g7ikx8voUBqWEzcpozJ5ZVBetJle9zpbgmLESgNLiU0OwJgmlQiTYf5a+4ciqPdY94EJNubdb/Q4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=LxNgOmsu; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="LxNgOmsu" X-UUID: 951785801c1b11f1a02d4725871ece0b-20260310 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=4cZtpNr2xeZJdyeS+qSCfwN53SQaiuSNWhMXvj97KgU=; b=LxNgOmsuCA+OBysOpOjLeRdPngXjdk2dJ2PcG5qayP314VIaP4rMNfhiwB/VkwdeOVJL3p2JJVOE+otzoJWy3f1qXsrOIohjXyGZRYcrZSwYR2mODKl5n61MPfh427ItEJK1TPbPidcGYAhvJKZkLb3Y0gXX3FAefxlba5h5CiE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.11,REQID:fae65ca9-f05d-4ffa-b4e8-3c9a10f18448,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:89c9d04,CLOUDID:88030d5c-a957-4259-bcca-d3af718d7034,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102|123|836|888|898,TC:-5,Content:0| 15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OSI:0 ,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 951785801c1b11f1a02d4725871ece0b-20260310 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 638698123; Tue, 10 Mar 2026 08:53:41 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Tue, 10 Mar 2026 08:53:40 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Tue, 10 Mar 2026 08:53:40 +0800 From: To: , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , , , , Ed Tsai Subject: [PATCH v2 0/2] ufs: add delay for VCC ramp-up stability Date: Tue, 10 Mar 2026 08:52:26 +0800 Message-ID: <20260310005230.4001904-2-ed.tsai@mediatek.com> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N From: Ed Tsai Hi, This patch series resolves a link stability issue found on our certain platforms where the VCC regulator has a slow ramp-up time. To fix this, a delay is needed after VCC is turned on. The solution is implemented in two parts: 1. Introduce the new host quirks, UFSHCD_QUIRK_VCC_ON_DELAY. 2. Apply in our new platform with UFS5 device to ensure the VCC is ready before we enable the clocks. Changes in v2: - Fix typos and wording issues. Ed Tsai (2): ufs: core: Add quirks for VCC ramp-up delay ufs: host: mediatek: Add VCC on delay for stability drivers/ufs/core/ufshcd.c | 12 ++++++++++++ drivers/ufs/host/ufs-mediatek.c | 11 +++++++++++ drivers/ufs/host/ufs-mediatek.h | 4 ++++ include/ufs/ufshcd.h | 6 ++++++ 4 files changed, 33 insertions(+) -- 2.45.2