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Tue, 10 Mar 2026 02:19:55 -0700 (PDT) Received: from wenstp920.tpe.corp.google.com ([2a00:79e0:201d:8:ee38:e01e:e888:6900]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a48a3b74sm16965190b3a.45.2026.03.10.02.19.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 02:19:55 -0700 (PDT) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno , Ryder Lee , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas Cc: Chen-Yu Tsai , Bartosz Golaszewski , linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 0/7] PCI: mediatek-gen3: add power control support Date: Tue, 10 Mar 2026 17:19:39 +0800 Message-ID: <20260310091947.2742004-1-wenst@chromium.org> X-Mailer: git-send-email 2.53.0.473.g4a7958ca14-goog Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi folks, This is v4 of my MediaTek PCIe gen3 controller driver power control support series. Changes since v3: - Link to v3: https://lore.kernel.org/all/20260302053109.1117091-1-wenst@chromium.org/ - Added two patches to move kernel setup code before controller setup code, and controller setup code before device setup code, as requested by Bjorn - Dropped dts patches as they are already merged I kept all the existing reviewed-by tags, since the changes to the existing patches aren't that big. Changes since v2: - Link to v2: https://lore.kernel.org/all/20260226092234.3859740-1-wenst@chromium.org/ - Made PCIE_MEDIATEK_GEN3 select PCI_PWRCTRL_SLOT, following existing examples I do wonder why the existing ones don't select PCI_PWRCTRL instead. As there are multiple providers, and now even the M.2 power sequencing driver, I think either we enable the common ones by default, or let the user pick and choose. Changes since v1: - Link to v1: https://lore.kernel.org/all/20260224071258.2654521-1-wenst@chromium.org/ - commit message for patch 3 was rewritten Jianjun Wang was dropped from the recipients as the email was bouncing. This series adds power control support to the MediaTek PCIe gen3 controller driver. This allows proper modeling of WiFi and NVMe adapters in the device tree and control over their power supplies. Patch 1 through 6 are cleanups and minor improvements to the driver. Patch 7 adds power control support using the new pwrctrl API to the PCIe controller driver. Please have a look. Thanks ChenYu [1] https://lore.kernel.org/linux-pci/20260224-pci-m2-e-v5-0-dd9b9501d33c@oss.qualcomm.com/ Chen-Yu Tsai (7): PCI: mediatek-gen3: Clean up mtk_pcie_parse_port() with dev_err_probe() PCI: mediatek-gen3: Move mtk_pcie_setup_irq() out of mtk_pcie_setup() PCI: mediatek-gen3: Move controller setup steps before PERST# control PCI: mediatek-gen3: Add error path for resume driver callbacks PCI: mediatek-gen3: Split out device power helpers PCI: mediatek-gen3: Disable device if further setup fails PCI: mediatek-gen3: Integrate new pwrctrl API drivers/pci/controller/Kconfig | 1 + drivers/pci/controller/pcie-mediatek-gen3.c | 223 +++++++++++--------- 2 files changed, 129 insertions(+), 95 deletions(-) -- 2.53.0.473.g4a7958ca14-goog