From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from casper.infradead.org (casper.infradead.org [90.155.50.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EBF039BFFA for ; Tue, 10 Mar 2026 14:12:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.50.34 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773151982; cv=none; b=Suv7nF2YMG3q15+AS4N/AP3GTbRbHRvNK3cKZHw4HlgpXtzpTaitjedgYf+OK6UsBCaRDIEbmFG/kaTQVGMZXMEgUDwfnA2jHqdN3QGUjLID/M7nQvBT96S8MZtXe94P/Tc/us5eth/QrEKmET1ZYAJAUW96J1AqXyt3GBV4Jsw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773151982; c=relaxed/simple; bh=N1wogYKpC+fjKWwhaKLVtDFBgFnrsddLnV4pXyzNRkE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=HDwAZZ2/z5ZDgpaRcFwazMlMAfNJC42qySJcxkFeGAMeAqmlD3JV1+7ndSL5iBGEz/kOB1rE/jXZ4hq+PjrxyR9eEKEgW061VwecYBv6rEDNQArF83vKX2jOERegCl0uxreav/oU5rfJfmDsczlincTMEAhZN0ty6jfoUmRs9o4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org; spf=none smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=FoF3pE5e; arc=none smtp.client-ip=90.155.50.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="FoF3pE5e" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=z0shXk+YjCoL/QWK5pUu2KStdh4YT8bJ7O5yxhuc/sU=; b=FoF3pE5eMJWx1DQV0Tpprt1M1k 60TH8pH4WQTLQ2pvIN7TyMqATZYw3UykL5b0dBpsMKwJovZ6DDkjFQDBsVJPcSEpXQYux/SNtjR9h pgnWpsmGto4jq5kHtFg5XmQrq0Hcxm+JkGonAHwE+LxUvn9FpBnwI0ZUHDkGiP21iuM4IPIbUBugN 0PbRVyFtNTmnBLp/Jd+y8AG1ursReuvH4IO3cfEW0nhuMRI8SGKkzVc99DrLFueOJ+qV75JDpKZ4H nRbLk5HOp/DUD98rGRsRrnHgCOFEKhgtxcQevHa2xTAR0CMRQ5XvwAQg2dBOanErlbLkoTiJn7Era DlJT2lIA==; Received: from 77-249-17-252.cable.dynamic.v4.ziggo.nl ([77.249.17.252] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.98.2 #2 (Red Hat Linux)) id 1vzxpQ-00000007xE8-2uDF; Tue, 10 Mar 2026 14:12:56 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id 5387A3007C4; Tue, 10 Mar 2026 15:12:55 +0100 (CET) Date: Tue, 10 Mar 2026 15:12:55 +0100 From: Peter Zijlstra To: David Laight Cc: Uros Bizjak , x86@kernel.org, linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: Re: [PATCH -tip 1/3] x86/fsgsbase: Remove unnecessary "memory" clobbers from FS/GS base accessors Message-ID: <20260310141255.GW1282955@noisy.programming.kicks-ass.net> References: <20260310082142.93834-1-ubizjak@gmail.com> <20260310102742.GU1282955@noisy.programming.kicks-ass.net> <20260310141104.4c57ea79@pumpkin> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260310141104.4c57ea79@pumpkin> On Tue, Mar 10, 2026 at 02:11:04PM +0000, David Laight wrote: > On Tue, 10 Mar 2026 11:27:42 +0100 > Peter Zijlstra wrote: > > > On Tue, Mar 10, 2026 at 09:21:22AM +0100, Uros Bizjak wrote: > > > The rdfsbase() and rdgsbase() helpers currently include a "memory" clobber > > > in their inline assembly definitions. However, the RDFSBASE and RDGSBASE > > > instructions only read the FS/GS base MSRs into a general-purpose register > > > and do not access memory. As such, the "memory" clobber is unnecessary. > > > > The point isn't that this accesses memory, but that prior or later > > accesses would end up at different memory locations (as would happen > > when setting the per-cpu segment. > > Don't they need a "memory" clobber to stop them being moved the other > side of a request to set the relevant register? > In effect the [fg]sbase register has to be treated like a memory location. Its a read, it doesn't matter. And no, IIRC the compilers are not allowed to re-order asm volatile, so as long as both the load and store of the segments register are asm volatile, those cannot get reordered.