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Wed, 11 Mar 2026 03:26:55 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2aeae222872sm19575245ad.18.2026.03.11.03.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Mar 2026 03:26:54 -0700 (PDT) From: Krishna Chaitanya Chundru Subject: [PATCH v3 0/5] PCI: qcom: Add D3cold support Date: Wed, 11 Mar 2026 15:56:45 +0530 Message-Id: <20260311-d3cold-v3-0-4d85dc7c2695@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAGVDsWkC/22MzQrCMBAGX6Xs2ZRkU2viyfcQD82fDbRGEw1K6 bubFtSLl4VZvpkJko3eJthXE0SbffLhUoBvKtB9dzlb4k1hQIpbhiiJ4ToMhignpUQmW6oUlPE 1Wuefa+h4Ktz7dA/xtXYzW75LoqUMxSeRGaHEGOG4o9oKbA4hpfr26AYdxrEuB5ZSxp+NbPe1s dhCKo4o2oY2/I89z/MbQhO+3+EAAAA= X-Change-ID: 20251229-d3cold-bf99921960bb To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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On Qualcomm platforms, PCIe host controllers are currently kept powered even when there are no active endpoints (i.e. all endpoints are already in PCI_D3hot). This prevents the SoC from entering deeper low‑power states such as CXPC. While PCIe D3cold support exists in the PCI core, host controller drivers lack a common mechanism to determine whether it is safe to power off the host bridge without breaking active devices or wakeup functionality. As a result, controllers either avoid entering D3cold or depend on rough, driver‑specific workarounds. This series addresses that gap. 1. Introduces pci_host_common_can_enter_d3cold(), a helper that determines whether a host bridge may enter D3cold based on downstream PCIe endpoint state. The helper permits D3cold only when all *active* endpoints are already in PCI_D3hot, and any wakeup‑enabled endpoint supports PME from D3cold. 2. Updates the Designware PCIe host driver to use this helper in the suspend_noirq() path, replacing the existing heuristic that blocked D3cold whenever L1 ASPM was enabled. 3. Enables D3cold support for Qualcomm PCIe controllers by wiring them into the DesignWare common suspend/resume flow and explicitly powering down controller resources when all endpoints are in D3hot. The immediate outcome of this series is that Qualcomm PCIe host bridges can enter D3cold when all endpoints are in D3hot. This is a necessary but not sufficient step toward unblocking CXPC. With this series applied, CXPC can be achieved on systems with no attached NVMe devices. Support for NVMe‑attached systems requires additional changes in NVMe driver, which are being worked on separately. Tested on: - Qualcomm Lemans EVK, Monaco & sc7280 platforms. Validation steps: - Boot without NVMe attach: * PCIe host enters D3cold during suspend * SoC is able to reach CXPC provided other drivers also remove their votes as part of suspend. Signed-off-by: Krishna Chaitanya Chundru --- Changes in v3: - Changed the function name from pci_host_common_can_enter_d3cold() to pci_host_common_d3cold_possible() (Mani). - Couple of nits for commit text, newlines etc(Mani). - Removed -ETIMEDOUT check and added -ENODEV & -EIO(Mani). - Link to v2: https://lore.kernel.org/r/20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com Changes in v2: - Updated the cover letter (Bjorn Andersson) - Add get_ltssm helper function to read LTSSM state from parf. - Allow D3cold if there is no driver enabled for a endpoint. - Added a seperate patch to make phy down in deinit part to avoid power leakage. - Revert icc bw voting if resume fails(Bjorn Andersson). - Link to v1: https://lore.kernel.org/r/20260128-d3cold-v1-0-dd8f3f0ce824@oss.qualcomm.com --- Krishna Chaitanya Chundru (5): PCI: host-common: Add helper to determine host bridge D3cold eligibility PCI: dwc: Use common D3cold eligibility helper in suspend path PCI: qcom: Add .get_ltssm() helper PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks PCI: qcom: Add D3cold support drivers/pci/controller/dwc/pcie-designware-host.c | 9 +- drivers/pci/controller/dwc/pcie-qcom.c | 165 +++++++++++++++------- drivers/pci/controller/pci-host-common.c | 47 ++++++ drivers/pci/controller/pci-host-common.h | 2 + 4 files changed, 167 insertions(+), 56 deletions(-) --- base-commit: b29fb8829bff243512bb8c8908fd39406f9fd4c3 change-id: 20251229-d3cold-bf99921960bb Best regards, -- Krishna Chaitanya Chundru