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Thu, 12 Mar 2026 08:56:44 -0700 (PDT) Received: from hu-mkshah-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c73cdf254acsm6067852a12.11.2026.03.12.08.56.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 08:56:43 -0700 (PDT) From: Maulik Shah Subject: [PATCH 0/5] x1e80100: Enable PDC wake GPIOs and deepest idle state Date: Thu, 12 Mar 2026 21:26:34 +0530 Message-Id: <20260312-hamoa_pdc-v1-0-760c8593ce50@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIADPismkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDY0Mj3YzE3PzE+IKUZF2LZBOTVHODJENTQ3MloPqCotS0zAqwWdGxtbU ARrT4RVsAAAA= X-Change-ID: 20260312-hamoa_pdc-8c44e70b1517 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad , Maulik Shah X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773331000; l=3532; i=maulik.shah@oss.qualcomm.com; s=20240109; h=from:subject:message-id; bh=aii1fPblRjNclJS2d8OX1hBWeOj56SYwnkO3sJwY7J0=; b=j6joHry2MQQKR2ZIes52GRlx/dwYfcyF+23+kSAxqG0PS031XjdvYlNq5q9mTnxm5l+H1FbQd zhAUXcXjqRCDdOh+bMj84a2bbb/JOu/7ADMfD/MRu6JfYvoiitxL9+C X-Developer-Key: i=maulik.shah@oss.qualcomm.com; a=ed25519; pk=bd9h5FIIliUddIk8p3BlQWBlzKEQ/YW5V+fe759hTWQ= X-Proofpoint-GUID: CNGKZSTDRmseqfOXL1NYnbn8ZLuSrId0 X-Authority-Analysis: v=2.4 cv=Cpays34D c=1 sm=1 tr=0 ts=69b2e23d cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=bCJDybkbam8vuuN2_HAA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-ORIG-GUID: CNGKZSTDRmseqfOXL1NYnbn8ZLuSrId0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEyMDEyOCBTYWx0ZWRfX1xu7eca5Dczs L2Rh34W2SD2ERy3gctAy1F2mgXnKECpu86VYvoYbXOosw11c58oJh59z32Uhy4zvKMYAMb/wrU5 6tcmGKPoZ+vgvoQPMZtA3IDBoBFVcqLw/GZL9BI6e/CTC0JI+6rNu2sqs+f+KkbBTQMVMwDrG6v I8iyYss0LrPPnvqZayEZtTjWyyrFdC/AlXbJNhNO0Ptu7Gma+ImBKNCRSoI3jQ2XkSP5HbtJGot VZQG3aIfGQfn8w2NpjS9AtavjBDmEi9GVsb23H171Si1zFWUe6XPk64n0Hau2zVE83uII/1IXXt whkrmPUy3F7dUr4Ki7JhCwhHm4W+4AtjNy45FYCoaZCCe3YB+3KoPq4UJWzKfyjxVoQ2Yv1kPpO ufUmRWniPooO18ZeI7lCmQVFL4TcQWLTPgjmu8lfCnkUpm6sxSrinNBqXBq0Mj+ZxitTSTHohvS 0PmHDl/EGbz9S4YyY9Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-12_02,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1011 lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603120128 There are two modes PDC irqchip can work in - pass through mode - secondary controller mode All PDC irqchip supports pass through mode in which both Direct SPIs and GPIO IRQs (as SPIs) are sent to GIC without latching at PDC, PDC only does inversion when needed for falling edge to rising edge or level low to level high, as the GIC do not support falling edge/level low interrupts. Newer PDCs (v3.0 onwards) also support additional secondary controller mode where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs still works same as pass through mode without latching at PDC even in secondary controller mode. All the SoCs defaulted to pass through mode with the exception of some x1e. x1e PDC may be set to secondary controller mode for builds on CRD boards whereas it may be set to pass through mode for IoT-EVK boards. There is no way to read which current mode it is set to and make PDC work in respective mode as the read access is not opened up for non secure world. There is though write access opened up via SCM write API to set the mode. As the linux only ever makes use of pass through mode, set the IRQ mask meant specifically for secondary controller mode to mask all the IRQs to be forwarded to GIC irrespective of the mode PDC is set to. Writing the mask is do not care when the PDC works in pass through mode, which is always the case except for some of x1e platforms. Configure PDC mode to pass through mode for all x1e based boards via SCM write. For successful write: - Nothing more to be done For unsuccessful write: - Inform TLMM to monitor GPIO IRQs (same as MPM) - Prevent SoC low power mode (CxPC) as PDC is not monitoring GPIO IRQs which may be needed to wake the SoC from low power mode. As the deepest idle state as the PDC can now wake up SoC from GPIOs and revert 602cb14e310a ("pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"). Note: For testing this series on x1e80100 CRD, interconnect nodes from SCM device are removed as PDC requires SCM APIs early in the boot up and interconnect nodes delays the probe of SCM device which results in early boot NULL pointer derefernce. Looking at documentation interconnect are added to get additional performance boost and are optional to add. Removing them for now allows this series to go through until proper fix from SCM device is found. The series has been tested on x1e80100 CRD with both old and new firmware and also on kaanapali. Signed-off-by: Maulik Shah --- Maulik Shah (5): arm64: dts: qcom: x1e80100: Remove interconnect from SCM device dt-bindings: interrupt-controller: qcom,pdc: Document reg and QMP irqchip/qcom-pdc: Configure PDC to pass through mode arm64: dts: qcom: x1e80100: Add deepest idle state Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now" .../bindings/interrupt-controller/qcom,pdc.yaml | 5 + arch/arm64/boot/dts/qcom/hamoa.dtsi | 19 +++- drivers/irqchip/Kconfig | 1 + drivers/irqchip/qcom-pdc.c | 119 +++++++++++++++++++-- drivers/pinctrl/qcom/pinctrl-x1e80100.c | 4 +- 5 files changed, 131 insertions(+), 17 deletions(-) --- base-commit: f90aadf1c67c8b4969d1e5e6d4fd7227adb6e4d7 change-id: 20260312-hamoa_pdc-8c44e70b1517 Best regards, -- Maulik Shah