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Thu, 12 Mar 2026 23:49:32 -0700 (PDT) Received: from hu-sumk-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c73eb97b41dsm936160a12.5.2026.03.12.23.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2026 23:49:32 -0700 (PDT) From: Sumit Kumar Subject: [PATCH 0/3] dmaengine: Add batched scatter-gather DMA support Date: Fri, 13 Mar 2026 12:19:24 +0530 Message-Id: <20260313-dma_multi_sg-v1-0-8fabb0d1a759@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAHSzs2kC/1WNwQ6CMBBEf4Xs2ZJuUTCe/A9DCJYFNqFUu0A0h H+34snLJG+SebOCUGASuCQrBFpY2I8R8JCA7euxI8VNZDDa5Br1WTWurtw8TFxJp6zBIj/prMi sgTh5BGr5tetuZeSeZfLhvdsX/LY/kdHZv2hBpRUezT2eEBXYXr1I+pzrwXrn0hhQbtv2AQN8W 02vAAAA X-Change-ID: 20260108-dma_multi_sg-c217650373c2 To: Krishna Chaitanya Chundru , Veerabhadrarao Badiganti , Subramanian Ananthanarayanan , Akhil Vinod , Manivannan Sadhasivam , Vinod Koul , Marek Szyprowski , Robin Murphy , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Kishon Vijay Abraham I , Bjorn Helgaas Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pci@vger.kernel.org, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, Sumit Kumar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1773384567; l=2678; i=sumit.kumar@oss.qualcomm.com; s=20250409; h=from:subject:message-id; bh=pvlk2gOPkIN+ITxicWXFZ618jc3EqUbu9jfuBJT+Pj8=; b=CJsyKHGdctf6eMe9FYY1OpAZhEpTLB18Re4kWKHiZ0+TKe0AV4X/h4B2qhl75oyvumt11XvKa T/JaOl/TpY9ArzGxVUQ0/u9VR0ZLcx4FAaInJyDJiUPuxoHqhv3XDfC X-Developer-Key: i=sumit.kumar@oss.qualcomm.com; a=ed25519; pk=3cys6srXqLACgA68n7n7KjDeM9JiMK1w6VxzMxr0dnM= X-Proofpoint-GUID: hkPCr_Wuw35ZdMZh7k2fXnfWaniIdSn9 X-Authority-Analysis: v=2.4 cv=BNG+bVQG c=1 sm=1 tr=0 ts=69b3b37e cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=f6ynY6_RdjVN_4bGfK8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: hkPCr_Wuw35ZdMZh7k2fXnfWaniIdSn9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzEzMDA1MiBTYWx0ZWRfXxeWsSRXSSXWh rKWQ+LgmdJipw9IXjzrY0crhzW432h98n5H0vxS8Z4wCQqzTxXtaIaT3YvCuxfUa3rxie6JnxNv m/HSdL570TpWuo83FW9zt6iwQucyp3BybF0Jy8TtozQo8iNk2nW1pcWRs20xCXHbgPnIQN8DPXu tYN+i+TdqYsk4BGH479CT2of/KKt6mMvNNq0gXJZhLz8CV+W1fMLk3efzumL/zjEDOES7uUjJEu hvhDElRxCpoLQcxStdJTwjj6m8q/ci3H7Qiq4REN1Z200IKJJ7wHvP8MMwKO6AzjRiDTljh07gv cBrLjcrIeuteXcRkMQJc95e+5AlO6JqNUXQx3yuQ/RlSKk1Y12CrsbXjzhLdjc0YxXgcF+XCP16 jEc6f66cX1wtNYP7SvWxmZLGS5lHQRNIRVfFhkBOx3R6ArE4DX/kvY1WsArVIhYEzLQOsJqc0wm XN1MzvUvzm3OkQioxNA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-13_01,2026-03-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 adultscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603130052 Synopsys DesignWare eDMA IP supports a linked-list (LL) mode where each LL item carries independent source and destination addresses. This allows multiple independent memory transfers to be described in a single linked list and submitted to the hardware as one DMA transaction, without any CPU intervention between items. The IP processes LL items strictly in order, guaranteeing that scatter-gather entries are never reordered. This series leverages that hardware capability to introduce a new dmaengine API — dmaengine_prep_batch_sg_dma() — for batching multiple independent buffers into a single DMA transaction. Each scatter-gather entry specifies both its own source (dma_address) and destination (dma_dst_address), enabling the eDMA hardware to process them as a single linked-list transaction. The primary use case is MHI endpoint ring caching. When an MHI ring wraps around, data spans two non-contiguous memory regions (tail and head portions). Previously this required two separate DMA transactions with two interrupts. With this series, both regions are submitted as a single batched transaction, reducing submission overhead and interrupt count. The series includes: 1. Core DMA engine API and DW eDMA driver implementation 2. PCI EPF MHI driver support for batched transfers 3. MHI endpoint ring caching optimization using batched reads Performance Benefits: -------------------- - Reduced DMA submission overhead for multiple transfers - Better hardware utilization through batched operations - Lower latency for ring wraparound scenarios Signed-off-by: Sumit Kumar --- Sumit Kumar (3): dmaengine: Add multi-buffer support in single DMA transfer PCI: epf-mhi: Add batched DMA read support bus: mhi: ep: Use batched read for ring caching drivers/bus/mhi/ep/ring.c | 43 +++++----- drivers/dma/dw-edma/Kconfig | 1 + drivers/dma/dw-edma/dw-edma-core.c | 40 ++++++++- drivers/dma/dw-edma/dw-edma-core.h | 3 +- drivers/pci/endpoint/functions/Kconfig | 1 + drivers/pci/endpoint/functions/pci-epf-mhi.c | 120 +++++++++++++++++++++++++++ include/linux/dmaengine.h | 29 ++++++- include/linux/mhi_ep.h | 3 + include/linux/scatterlist.h | 7 ++ kernel/dma/Kconfig | 3 + 10 files changed, 224 insertions(+), 26 deletions(-) --- base-commit: f0b9d8eb98dfee8d00419aa07543bdc2c1a44fb1 change-id: 20260108-dma_multi_sg-c217650373c2 Best regards, -- Sumit Kumar