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Sun, 15 Mar 2026 04:17:17 -0700 (PDT) Received: from j0sh1x-MS-7A34.lan ([2001:9e8:46a7:9a00:6d34:d2d4:e925:2b8d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48557777105sm110694825e9.4.2026.03.15.04.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Mar 2026 04:17:16 -0700 (PDT) From: j0sh1x To: tglx@kernel.org Cc: linux-kernel@vger.kernel.org, subsystem@vger.kernel.org, dominikkobinski314@gmail.com, j0sh1x Subject: [PATCH 1/5] dt-bindings: irq: Add Qualcomm MSM VIC binding Date: Sun, 15 Mar 2026 12:17:01 +0100 Message-ID: <20260315111705.118544-1-aljoshua.hell@gmail.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Signed-off-by: j0sh1x --- .../interrupt-controller/qcom,msm-vic.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml new file mode 100644 index 000000000000..5bf281f72fe0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 +# qualcomm,msm-vic.yaml - Device Tree binding for Qualcomm MSM VIC interrupt controller + +description: > + Qualcomm MSM VIC (Vector Interrupt Controller). This interrupt controller + handles normal and wakeup interrupts and supports mapping to the + Qualcomm SMSM system. + +compatible: ["qcom,msm-vic"] + +properties: + interrupt-controller: + description: "Identifies this node as an interrupt controller" + required: true + type: boolean + + #interrupt-cells: + description: "Specifies the number of cells needed to encode an interrupt" + required: true + type: integer + default: 1 + + reg: + description: "Base address and size of the VIC registers" + required: true + type: reg + + num-irqs: + description: "Total number of interrupts supported by this VIC" + required: true + type: integer + + num-gpio-irqs: + description: "Number of GPIO interrupts routed through this VIC" + required: true + type: integer + + vic-num-regs: + description: "Number of VIC register banks" + required: true + type: integer + + irq-mapping: + description: + Mapping of VIC IRQ numbers to SMSM wakeup channels. Each mapping + consists of two integers: . + "SMSM_FAKE_IRQ" can be used for virtual/fake wakeup interrupts. + required: true + type: list + items: + - vic-irq: integer + smsm-channel: integer + +examples: + - | + #include + intc: interrupt-controller@ac000000 { + compatible = "qcom,msm-vic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xac000000 0x1000>; + num-irqs = <64>; + num-gpio-irqs = <165>; + vic-num-regs = <2>; + irq-mapping = < + 17 1 /* INT_MDDI_EXT -> SMSM 1 */ + 16 2 /* INT_MDDI_PRI -> SMSM 2 */ + 18 3 /* INT_MDDI_CLIENT -> SMSM 3 */ + 15 4 /* INT_USB_OTG -> SMSM 4 */ + 0 SMSM_FAKE_IRQ /* INT_A9_M2A_0 -> SMSM_FAKE_IRQ */ + >; + } \ No newline at end of file -- 2.51.0