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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FisliZFk94Av2Iu2E739GUUoc8xo4wp+Vq1xGgDBaAoqCqEBqOX3RssQ+E+s7bdJfssjD24E5wYA6G5gz/FctJkG5hEPi+sF/KsCOS+BtlgpKlw3nwW8pTxJogr5BLer4jRmOkeBJonSfaWSxgNdO1H4amgUu+uS8FA9vSC3YMJZvBURXWfwU7q26RpoME2iWAdgk245FwIgDCE9i4pRZmIKktC1ZHLd1eRO+5m0wlFJUpL0FsqbPlk6MEzYDhuVpEg38uljurnATJbK/10/RP/IXL5j1eNee3FULAU/I6fH+tOUWjoSP80D/pe5Wb8+gBOpf3DZIYvpcfJ9B588Sj8iuwJ079n6UwwUDeo9KITu9zaMglFYIZX0CCG7NOTcWyJZSyTQyK6HWWcTaOUen/SHPzCpmyyGdEBWAyb4HcsQIwqEyqt9nooR6xL23kza X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2026 17:18:50.0305 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c1eb1c2f-11ee-4bf7-4d9b-08de83801738 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD76.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA4PR12MB9788 This series adds support for GPCDMA in Tegra264 with additional support for separate stream ID for each channel. Tegra264 GPCDMA controller has changes in the register offsets and uses 41-bit addressing for memory. Add changes in the tegra186-gpc-dma driver to support these. v2->v3: - Add description for iommu-map property and update commit descriptions. - Use enum for compatible string instead of const. - Remove unused registers from struct tegra_dma_channel_regs. - Use devm_of_dma_controller_register() to register the DMA controller. - Remove return value check for mask setting in the driver as the bitmask value is always greater than 32. v1->v2: - Fix dt_bindings_check warnings - Drop fallback compatible "nvidia,tegra186-gpcdma" from Tegra264 DT - Use dma_addr_t for sg_req src/dst fields and drop separate high_add variable and check for the addr_bits only when programming the registers. - Update address width to 39 bits for Tegra234 and before since the SMMU supports only up to 39 bits till Tegra234. - Add a patch to do managed DMA controller registration. - Describe the second iteration in the probe. - Update commit descriptions. Akhil R (9): dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional dmaengine: tegra: Make reset control optional dmaengine: tegra: Use struct for register offsets dmaengine: tegra: Support address width > 39 bits dmaengine: tegra: Use managed DMA controller registration dmaengine: tegra: Use iommu-map for stream ID dmaengine: tegra: Add Tegra264 support arm64: tegra: Add iommu-map and enable GPCDMA in Tegra264 .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 34 +- .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi | 4 + arch/arm64/boot/dts/nvidia/tegra264.dtsi | 3 +- drivers/dma/tegra186-gpc-dma.c | 435 +++++++++++------- 4 files changed, 292 insertions(+), 184 deletions(-) -- 2.50.1