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[61.221.208.111]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82a6bef5ed8sm5660824b3a.57.2026.03.18.23.15.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 23:15:41 -0700 (PDT) From: "Adrian Huang (Lenovo)" To: Joerg Roedel , Suravee Suthikulpanit Cc: Will Deacon , Robin Murphy , iommu@lists.linux.dev, linux-kernel@vger.kernel.org, ahuang12@lenovo.com, "Adrian Huang (Lenovo)" Subject: [PATCH 0/2] iommu/amd: Preserve x2APIC and MSI support when amd_iommu=off Date: Thu, 19 Mar 2026 14:15:05 +0800 Message-Id: <20260319061507.541-1-adrianhuang0701@gmail.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit [Overview] This patch series modifies the behavior of the amd_iommu=off kernel parameter to ensure that x2APIC and MSI domain allocation remain functional, even when DMA translation is disabled. Currently, on AMD systems, specifying amd_iommu=off completely shuts down the IOMMU subsystem. This causes the system to disable x2APIC and fall back to physical flat mode, which limits the system to 255 APIC IDs. On high-core-count systems (e.g., 448 cores), this results in a significant number of CPUs failing to bring up. Furthermore, dynamically added PCI devices (such as SR-IOV VFs) fail to associate with the correct MSI domain, leading to IOMMU fault events and kernel warnings. [Motivation] On Intel platforms, intel_iommu=off only disables DMA translation while keeping the necessary interrupt remapping infrastructure active to support x2APIC and high CPU counts. This series brings the AMD IOMMU driver in line with this behavior, ensuring stability on modern, large-scale hardware. [Patch Summary] Patch 1: Adjusts the amd_iommu=off semantics to keep x2APIC enabled. It ensures that the kernel can bring up all available CPUs on large systems by maintaining x2APIC ops instead of falling back to physical flat mode. Patch 2: With applying "Patch 1", patch 2 ensures the PCI bus notifier is registered even when amd_iommu=off is used. This allows hotplugged devices or SR-IOV VFs to be correctly assigned to the IOMMU interrupt remapping domain, preventing INVALID_DEVICE_REQUEST faults and MSI activation failures. [Verification] Testing was performed on a 448-core Lenovo ThinkSystem server. All 448 CPUs are successfully initialized; SR-IOV VFs are created and assigned interrupts without faults. Adrian Huang (Lenovo) (2): iommu/amd: Keep x2apic enabled when appending amd_iommu=off iommu/amd: Register PCI bus notifier when appending amd_iommu=off drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/init.c | 81 ++++++++++++++++++++++++++++++----- drivers/iommu/amd/iommu.c | 14 ++++++ 3 files changed, 86 insertions(+), 10 deletions(-) -- 2.47.3