From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9C35C3A9DA1 for ; Fri, 20 Mar 2026 11:30:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774006248; cv=none; b=H+zZCBjJrzPSez6L33w8qlrbvSP7t8pksp6qxh4OdY8SFCQro3NlEnVhWZNecStrPBsUTRl6hipvcbeWcN+/w58Zzf3GCs5evpf1pFXoaj0YZ1E7LsrWWVHyIagm4bZAM9RrxOpDU+SLSjy9zPk/9QNLL7iJD6Qgeyo79N+9oz8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774006248; c=relaxed/simple; bh=9bOMEomgnQeAgR1Pt1OhfbeszYhex6v9fEOzuAnZ40c=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=Hi8joYCubK9xVUIzwvHFrnODptQQJOQABH1xl+ZKAWVqBwAYKpuz5h41Uc4Z+BBW78+Rm0vO4rZVR9h4LLzuIS5XOiBXnpvkuGztZQrxnx7EydKJjFAVSCyU7wlwvhxeyQhaagCjzjgvOEwnlQJTIT91DTpSfsDgbEMwsrsahrA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C73861682; Fri, 20 Mar 2026 04:30:30 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3CC673F7BD; Fri, 20 Mar 2026 04:30:35 -0700 (PDT) From: Mark Rutland To: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, peterz@infradead.org, tglx@kernel.org, vladimir.murzin@arm.com, will@kernel.org Cc: ada.coupriediaz@arm.com, linux-kernel@vger.kernel.org, luto@kernel.org, mark.rutland@arm.com, ruanjinjie@huawei.com Subject: [PATCH 0/2] arm64/entry: Fix involuntary preemption exception masking Date: Fri, 20 Mar 2026 11:30:24 +0000 Message-Id: <20260320113026.3219620-1-mark.rutland@arm.com> X-Mailer: git-send-email 2.30.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi all, Since the move to generic IRQ entry, arm64's involuntary kernel preemption logic has been subtly broken, and preemption can lead to tasks running with some exceptions masked unexpectedly. Patch 1 describes the gory details, but the gist is that due to the way exceptions work on arm64 architecturally, and due to the number of independently maskable exceptions, some aspects of the generic irq entry code aren't a great fit, and arm64 needs to manage more of the sequencing and state management itself. Doing so will also make it possible to implement new stuff in the near future (e.g. architectural NMI). Patch 2 is purely a cleanup atop patch 1. Thomas, Peter, I have some questions at the end of the patch 1 commit message, but otherwise I hope this looks good to you. I'm assuming that this should go via the arm64 tree, so I'm looking for your acks on both patches. Mark. Mark Rutland (2): arm64/entry: Fix involuntary preemption exception masking arm64/entry: Remove arch_irqentry_exit_need_resched() arch/Kconfig | 3 +++ arch/arm64/Kconfig | 1 + arch/arm64/include/asm/entry-common.h | 27 --------------------------- arch/arm64/kernel/entry-common.c | 27 +++++++++++++++++++++++++++ kernel/entry/common.c | 20 ++++---------------- 5 files changed, 35 insertions(+), 43 deletions(-) -- 2.30.2