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The controller is similar to previous generations, but the register fields are widened, the depth is made configurable, and the enable bit moves to a different spot. This series adds only basic support with fixed depth -- configurable depth will come later. The series uses the nvidia,tegra264-pwm compatible string. Bindings for this are added in Thierry's series https://lore.kernel.org/linux-tegra/20260320234056.2579010-1-thierry.reding@kernel.org/ Thanks, Mikko --- Mikko Perttunen (4): pwm: tegra: Modify read/write accessors for multi-register channel pwm: tegra: Parametrize enable register offset pwm: tegra: Parametrize duty and scale field widths pwm: tegra: Add support for Tegra264 Yi-Wei Wang (1): pwm: tegra: Avoid hard-coded max clock frequency drivers/pwm/pwm-tegra.c | 141 +++++++++++++++++++++++++++++++++--------------- 1 file changed, 98 insertions(+), 43 deletions(-) --- base-commit: b7cac19bc4780fe1156b217a1c5c96a3e23b275b change-id: 20260303-t264-pwm-57e10d039df1