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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b0836556f6sm219985805ad.49.2026.03.24.22.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Mar 2026 22:43:56 -0700 (PDT) From: Yingchao Deng Subject: [PATCH v7 0/4] Add Qualcomm extended CTI support Date: Wed, 25 Mar 2026 13:43:43 +0800 Message-Id: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAA92w2kC/3WMywrCMBBFf6XM2pQ0fURd+R9SJKRTO2AbzcRQK fl3Y/duLpwL52zA6AkZzsUGHiMxuSWDPhRgJ7PcUdCQGZRUnaxVI3ANuAw43GwgoaXu6qNFxBN CVp4eR1r33LXPPBEH5z97Perf+ycUtZDCGNPVY9VWpm0ujrl8vc3Dunku80CfUvoCvMwESK8AA AA= To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Jinlong Mao , Tingwei Zhang , Jie Gan , quic_yingdeng@quicinc.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774417433; l=4099; i=yingchao.deng@oss.qualcomm.com; s=20260324; h=from:subject:message-id; bh=hfNnIy09gQAwSpJazpfbAL4y9Aen7kUVg/JvfuXPoDw=; b=P4Jlubq3F4tt8/Su0mQVOpNpkE+VV20omltfz3xu3W51uzkHxUe654MtS2uJ34J8CmpQBAUpt iSFqlOfenO6Czfzxy7Q3Z/34tGMKShMlhs6dRaVFyOXAObfng12bGfz X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=5tp504LR96W2IVT3sAbRCqWtoG16CxJVUnXJSfU8NlQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI1MDAzOCBTYWx0ZWRfX024VJCGA9rl7 zJBoWlhJrZWQcIMY6v84+Jbd4nJQPtZkcs6ez5Oy5F2XA/C1xdti2PLA1ETv/6osm+Q0KN4YFdM y7CMadZaR8htkguepggQnOYzKVz3PfM3sTxZHP2f/lfuiw1bN1Hz55hGzx/xPINEk6dGxZULiN+ cp9nU2GAUsWclOS1SXsxELIIpzJ+9IfPV/meUQjRjt0DaNdjTTNPeuPRFFqaOfsLn7E9zo7gHqb 7hN3a11mAVs5MYgFxh668dEI7p2ZzPcK/o19zm6kyM6BneE2Nye4/C8GQtMWJPSuYFjLFJkkqiI DYlmUT1eQQuyrm+IFKryM1/1Z4futQPY5IdE+l0T+74eU7komW3+MP1ey8KMzhaNlcolDi9NRcC ui/u0W7s1/iiAvcpg9QKE1GmzGUSOMqHFgajoiFPhRg7JLCAB+s4FFKELOQaHUCJVdSVv7wTIgr +bV6Tp/lar1PsJLC15g== X-Authority-Analysis: v=2.4 cv=P5M3RyAu c=1 sm=1 tr=0 ts=69c3761e cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=ivfPcWm90DfOTC_Zvf4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 0cA5KFawW_c567SN37qMR3ScNb4x_P5O X-Proofpoint-GUID: 0cA5KFawW_c567SN37qMR3ScNb4x_P5O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-25_02,2026-03-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 spamscore=0 bulkscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250038 The Qualcomm extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. Qualcomm extended CTI supports up to 128 triggers. And some of the register offsets are changed. The commands to configure CTI triggers are the same as ARM's CTI. Prerequisites: This series depends on the following CoreSight fix: [PATCH v2 1/1] coresight: fix issue where coresight component has no claimtags Link: https://lore.kernel.org/all/20251027223545.2801-2-mike.leach@linaro.org/ Changes in v7: 1. Split the extended CTI support into smaller, logically independent patches to improve reviewability. 2. Removed the dual offset-array based register access used in v6 for standard and Qualcomm CTIs. Register addressing is now unified through a single code path by encoding the register index together with the base offset and applying variant-specific translation at the final MMIO access point. 3. Removed ext_reg_sel, extend the CTI sysfs interface to expose banked register instances on Qualcomm CTIs only. Numbered sysfs nodes are hidden on standard ARM CTIs, and on Qualcomm CTIs their visibility is derived from nr_trig_max (32 triggers per bank), ensuring that only registers backed by hardware are exposed. Link to v6 - https://lore.kernel.org/all/20251202-extended_cti-v6-0-ab68bb15c4f5@oss.qualcomm.com/ Changes in v6: 1. Rename regs_idx to ext_reg_sel and add information in documentation file. 2. Reset CLAIMSET to zero for qcom-cti during probe. 3. Retrieve idx value under spinlock. 4. Use yearless copyright for qcom-cti.h. Link to v5 - https://lore.kernel.org/all/20251020-extended_cti-v5-0-6f193da2d467@oss.qualcomm.com/ Changes in v5: 1. Move common part in qcom-cti.h to coresight-cti.h. 2. Convert trigger usage fields to dynamic bitmaps and arrays. 3. Fix holes in struct cti_config to save some space. 4. Revert the previous changes related to the claim tag in cti_enable/disable_hw. Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/ Changes in v4: 1. Read the DEVARCH registers to identify Qualcomm CTI. 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and coresight_cti_reg_store() functions accordingly. 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h. Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/ Changes in v3: 1. Rename is_extended_cti() to of_is_extended_cti(). 2. Add the missing 'i' when write the CTI trigger registers. 3. Convert the multi-line output in sysfs to single line. 4. Initialize offset arrays using designated initializer. Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/ Changes in V2: 1. Add enum for compatible items. 2. Move offset arrays to coresight-cti-core Signed-off-by: Yingchao Deng --- Yingchao Deng (4): coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays coresight: cti: encode trigger register index in register offsets coresight: cti: add Qualcomm extended CTI identification and quirks coresight: cti: expose banked sysfs registers for Qualcomm extended CTI drivers/hwtracing/coresight/coresight-cti-core.c | 114 ++++++++++++++++----- .../hwtracing/coresight/coresight-cti-platform.c | 16 +-- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 75 ++++++++++++-- drivers/hwtracing/coresight/coresight-cti.h | 30 ++++-- drivers/hwtracing/coresight/qcom-cti.h | 65 ++++++++++++ 5 files changed, 247 insertions(+), 53 deletions(-) --- base-commit: 5bca1f031b65a4a8caf700537cbbc770252af475 change-id: 20260324-extended_cti-707638ceee9e Best regards, -- Yingchao Deng