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Fri, 27 Mar 2026 12:30:35 -0700 (PDT) Received: from debian.killsync.com ([103.85.207.6]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82ca8466e01sm25136b3a.20.2026.03.27.12.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 12:30:34 -0700 (PDT) From: aravindanilraj0702@gmail.com To: broonie@kernel.org, linux-sound@vger.kernel.org Cc: cezary.rojewski@intel.com, liam.r.girdwood@linux.intel.com, peter.ujfalusi@linux.intel.com, yung-chuan.liao@linux.intel.com, ranjani.sridharan@linux.intel.com, kai.vehmanen@linux.intel.com, pierre-louis.bossart@linux.dev, perex@perex.cz, tiwai@suse.com, linux-kernel@vger.kernel.org, Aravind Anilraj Subject: [PATCH 0/3] ASoC: Intel: Fix MCLK leaks in Date: Fri, 27 Mar 2026 15:29:59 -0400 Message-ID: <20260327193002.423897-1-aravindanilraj0702@gmail.com> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Aravind Anilraj In three Intel ASoC board drivers, the EVENT_ON path in platform_clock_control() enables MCLK via clk_prepare_enable() but fails to call clk_disable_unprepare() on subsequent error paths, leaking the clock reference. Fix this across all three affected drivers. Aravind Anilraj (3): ASoC: Intel: bytcr_rt5640: Fix MCLK leak on platform_clock_control error ASoC: Intel: bytcr_rt5651: Fix MCLK leak on platform_clock_control error ASoC: Intel: cht_bsw_rt5672: Fix MCLK leak in platform_clock_control sound/soc/intel/boards/bytcr_rt5640.c | 1 + sound/soc/intel/boards/bytcr_rt5651.c | 3 ++- sound/soc/intel/boards/cht_bsw_rt5672.c | 4 +++- 3 files changed, 6 insertions(+), 2 deletions(-) -- 2.47.3