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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: iV0kQpdpiGajLtmjgVc+M/1g4y6HrrHp9VbSg4+Sr2+jYON4PsZcb2/6sFMj/05+rF7ERpyf/B9BORHGZ8HoYEzcNOfUQa58+HMDM+zQlKV5k9WFLlSWJ2yZbSdxD+G2Q5GCYmy2MEKUFbJEZysjpO/RJC13LmKXsKVqhaYTTQvue4B9yeGMqBrYvbD8AcHQTI/nMEvBx7+cavMjThYA9dxDqqqY1pcojrZ2XtrgamuYwK9rr7efUjM86lgzWZp1LaOafogrLH2LjpuZoFuA4EUV+QiwYtCotJmlbD3nZvpqRiGzjcWjb7nF7UoGwUV4AESaLx470uliMhGluNuCr55jleBmaF0WRi+ulzsujU7KGY8Ecfg8AppQNsXz22F+2frz/E+VOb3D70IN6iNJPvAbnxXQD6Cy0baO+fdfTpGMnYoUUYNXlbpq4ORaiIop X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2026 08:42:40.6687 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d577c997-5bf0-45e0-74f7-08de8e384dc8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017090.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8976 AMD IOMMU introduces the vIOMMU feature, which provides partial hardware acceleration when implementing Guest IOMMUs. This feature provides acceleration for guest Command Buffer, Event Log, and PPR Log. This eliminates the CPU overhead needed for the supporting HV intercepts and reduces the latency of these operations. When a guest attempts to access guest IOMMU MMIO registers with offsets between 8KB and 12KB (i.e. 3rd 4K region) such as the Command Buffer, Event Log and PPR Log head and tail pointer registers, this is serviced directly by the IOMMU. When the IOMMU accesses a Command Buffer, PPR Log or a COMPLETION_WAIT store location in memory, it directly accesses guest physical memory. The HV/VMM continues trap and to emulate the IOMMU configuration MMIO registers between 0KB and 4KB (i.e. 1st 4K region), which are primarily used during initialization. Additionally, the HV must initialize the vIOMMU feature, map MMIO resources between the VMs and the IOMMU, manage additional supporting data structures in memory (e.g. GPA->SPA translation DTE, Device ID and Domain ID mapping tables), and allocate/map vIOMMU Private Address region used as backing storage memory for the IOMMU. Support for new IOMMU command and events specifically for vIOMMU are also added. Guest IOMMUs are IOMMUs exposed to VMs with additional support from VMM (QEMU) to generate guest ACPI IVRS table and define guest PCI topology for IOMMU and pass-through VFIO devices, which are not covered by this series. For more detail, please section vIOMMU of the AMD IOMMU Specification[1]. This series is implemented on top of IOMMUFD vIOMMU, vDevice, and HW-queue framework. It is organized into the following subset of patches: Patch 1-3 : Preparatory patches Patch 4-5 : Introduce IOMMUFD vIOMMU support for AMD Patch 6-8 : Introduce AMD vIOMMU VF MMIO and VFCtrl MMIO Patch 9-13 : Introduce AMD vIOMMU Private Address support Patch 14-16 : Introduce IOMMUFD vDevice support for AMD Patch 17 : Introduce AMD vIOMMU Translation DTE Patch 18-21 : Introduce IOMMUFD hw_queue support for AMD Patch 22 : Enable AMD vIOMMU support Upcoming Series: * Add Extended Interrupt Remapping support (for guest Event / PPR log interrupts) * Add Guest Event Injection support Note: * This series is rebased on top of v6.19. See [2] for git repo. [1] IOMMU Specification: https://docs.amd.com/v/u/en-US/48882_3.10_PUB [2] GIT Repo: https://github.com/AMDESE/linux-iommu/tree/wip/linux-6.19-amd-viommu_upstream_v1 Thank you, Suravee Suravee Suthikulpanit (22): iommu/amd: Make amd_iommu_completion_wait() non-static iommu/amd: Introduce vIOMMU-specific events and event info iommu/amd: Detect and initialize AMD vIOMMU feature iommu/amd: Introduce IOMMUFD vIOMMU support for AMD iommu/amd: Introduce vIOMMU Guest-ID (GID) iommu/amd: Map vIOMMU VF MMIO and VF Control MMIO regions iommu/amd: Add support for AMD vIOMMU VF MMIO region iommu/amd: Introduce Reset vMMIO Command iommu/amd: Introduce domain for IOMMU Private Address (IPA) region iommu/amd: Assign IOMMU Private Address domain to IOMMU iommu/amd: Allocate and map vIOMMU private regions iommu/amd: Add helper functions to manage private address region for each VM iommu/amd: Add helper functions to manage DevID / DomID mapping tables iommu/amd: Introduce IOMMUFD vDevice support for AMD iommu/amd: Introduce helper function for updating domain ID mapping table iommu/amd: Introduce helper function for updating device ID mapping table iommu/amd: Introduce vIOMMU Translation DTE iommufd: Introduce iommufd_viommu_ops.hw_queue_init iommu/amd: Add support for vIOMMU HW queues initialization iommufd: Introduce vIOMMU option via IOMMU_OPTION ioctl iommu/amd: Handle set/get option for AMD vIOMMU hw_queue iommu/amd: Introduce logic to check and enable vIOMMU feature drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu.h | 26 ++ drivers/iommu/amd/amd_iommu_types.h | 78 ++++ drivers/iommu/amd/amd_viommu.h | 67 ++++ drivers/iommu/amd/init.c | 27 +- drivers/iommu/amd/iommu.c | 204 ++++++++-- drivers/iommu/amd/iommufd.c | 170 ++++++++ drivers/iommu/amd/nested.c | 18 + drivers/iommu/amd/vfctrl_mmio.c | 145 +++++++ drivers/iommu/amd/viommu.c | 498 ++++++++++++++++++++++++ drivers/iommu/iommufd/ioas.c | 2 +- drivers/iommu/iommufd/iommufd_private.h | 1 + drivers/iommu/iommufd/main.c | 6 +- drivers/iommu/iommufd/viommu.c | 143 +++++-- include/linux/iommufd.h | 10 +- include/uapi/linux/iommufd.h | 25 +- 16 files changed, 1343 insertions(+), 79 deletions(-) create mode 100644 drivers/iommu/amd/amd_viommu.h create mode 100644 drivers/iommu/amd/vfctrl_mmio.c create mode 100644 drivers/iommu/amd/viommu.c -- 2.34.1